UPD17062 datasheet(208/298 Pages) RENESAS

208 / 298 page

206

µPD17062

16.2

CLOCK COUNTER

The clock counter is a wrap around counter that counts the clock of the shift clock pin (P0A1/SCL pin for

CH0, P0A2/SCK pin for CH1) of the currently selected serial interface. The clock counter counts the shift clock

from 1 to 9 repeatedly. The initial value of the counter is 0. The counter is incremented by 1 each time the

clock rising edge is detected. Once the counter has been incremented to 9, the counter is reset to 1, after which

it is again incremented in the same way.

In the following cases, the clock counter is reset to 0.

(1) In two-wire bus mode

(a) At power-on reset

(b) When a STOP instruction is executed and the system is clock stopped

(d) When the serial interface operation mode is switched from two-wire bus mode to serial I/O mode

(2) In serial I/O mode

(a) At power-on reset

(b) When a STOP instruction is executed and the system clock is stopped

(d) When the serial interface operation mode is switched from serial I/O mode to two-wire bus mode

Whether the contents of the clock counter became 8 or 9 can be tested in the software by the status register.

A request to stop the clock in either transmission mode or reception mode in two-wire bus mode can be

handled by the wait register.

UPD17062 Fiches technique(PDF) 208 Page - Renesas Technology Corp