AD9985ASLASHPCB datasheet(25/32 Pages) AD

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AD9985A

Rev. 0 | Page 25 of 32

Table 38. Detected Coast Input Polarity Status

Polarity Status

Result

Coast polarity negative

Coast polarity positive

This indicates that Bit 1 of Register 5 is the 4:2:2

output mode select bit.

4:2:2 Output Mode Select

A bit that configures the output data in 4:2:2 mode.

This mode can be used to reduce the number of data

lines used from 24 down to 16 for applications using

YUV, YCbCr, or YPbPr graphics signals. A timing

diagram for this mode is shown in Figure 11.

Recommended input and output configurations are

shown in Table 39 and Table 40.

Table 39. 4:2:2 Output Mode Select

Select

Output Mode

4:2:2

4:4:4

Table 40. 4:2:2 Input/Output Configuration

Channel

Input Connection

Output Format

Red

U/V

Green

Blue

High impedance

Extra PLL Divider

A bit that can add an additional divide-by-2 into the

PLL divide ratio. Enabling this function at pixel

frequencies below 20 MHz can result in improved PLL

jitter performance, as it allows the VCO to run at a

higher frequency, resulting in lower jitter.

Table 41. PLL VCO Divide

Select

PLL Divider

Off

Extra divide-by-2

6-5

SOGIN Bandwidth

Two bits that can control the bandwidth of the sync-

on-green input (SOGIN). In most applications, the

SOGIN bandwidth should be set to its maximum

(300 MHz). When there is excessive noise on SOGIN,

reducing the bandwidth can help suppress the noise.

Table 42. SOGIN Bandwidth

Select

Pulses Filtered

300 MHz

01 or 10

13 MHz

6.5 MHz

Analog Input Bandwidth

This bit controls the bandwidth of the red, green,

and blue analog inputs. In most applications, the

analog input bandwidth should be set to its maximum

(300 MHz). When there is excessive noise on the

analog inputs, reducing the bandwidth can help

suppress the noise.

Table 43. Anti-Aliasing Filter

Select

Input Bandwidth

300 MHz

7 MHz

7:0

Red Target Code

This specifies the targeted value of the final offset

for the red channel when auto-offset is used

(Register 0x1D, Bit 7 = 1). Default is 4.

7:0

Green Target Code

This specifies the targeted value of the final offset

for the green channel when auto-offset is used

(Register 0x1D Bit 7 = 1). Default is 4.

7:0

Blue Target Code

This specifies the targeted value of the final offset

for the blue channel when auto-offset is used

(Register 0x1D, Bit 7 = 1). Default is 4.

Auto-Offset Enable

Enables the auto-offset circuitry. Default is 0.

Hold Auto-Offset

Holds the offset output of the auto-offset at the

current value. Default is 0.

1:0

Update Mode

Changes the update rate of the auto-offset.

Default is 10.

Table 44. Auto-Offset Update Rate

Update Mode

Auto-Offset Update Timing

Every clamp cycle

Every 16 clamp cycles

Every 64 camp cycles

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