AD9985ASLASHPCB datasheet(13/32 Pages) AD

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AD9985A

Rev. 0 | Page 13 of 32

the output of each ADC during the back porch of the input

signals, the AD9985A can self-adjust to eliminate any offset

errors in its own ADC channels, as well as any offset errors

present on the incoming graphics or video signals.

To activate the auto offset mode, set Register 0x1D, Bit 7 to 1.

Next, the target code registers (0x19 through 0x1B) must be

programmed. The values programmed into the target code

registers should be the output code desired from the AD9985A

during the back porch reference time. For example, for RGB

signals, all three registers are normally programmed to code 1,

while for YPbPr signals, the green (Y) channel is normally

programmed to code 1, and the blue and red channels (Pb and

Pr) are normally set to 128. Any target code value between 1

and 254 can be set, although the AD9985A’s offset range may

not be able to reach every value. Intended target code values

range from (but are not limited to) 1 to 40 when ground

clamping, and 90 to 170 when midscale clamping.

The ability to program a target code for each channel gives

users a large degree of freedom and flexibility. While in most

cases all channels are set either to 1 or 128, the flexibility to

select other values allows the possibility of inserting intentional

skews between channels. It also allows the ADC range to be

skewed so that voltages outside of the normal range can be

digitized. For example, setting the target code to 40 allows the

sync tip, which is normally below black level, to be digitized and

evaluated.

Lastly, when in auto offset mode, the manual offset registers

(0x0B to 0x0D) have new functionality. The values in these

registers are digitally added to the value of the ADC output. The

purpose of doing this is to match a benefit that is present with

manual offset adjustment. Adjusting these registers is an easy

way to make brightness adjustments. Although some signal

range is lost with this method, it has proven to be a very

popular function. In order to be able to increase and decrease

brightness, the values in these registers in this mode are signed

twos complement. The digital adder is only used in auto offset

mode. Although it cannot be disabled, setting the offset

registers to all 0s effectively disables it by always adding 0.

SYNC-ON-GREEN

The sync-on-green input operates in two steps. First, it sets a

baseline clamp level off of the incoming video signal with a

negative peak detector. Second, it sets the sync trigger level to a

programmable level (typically 150 mV) above the negative

peak. The sync-on-green input must be ac-coupled to the green

analog input through its own capacitor, as shown in Figure 5.

The value of the capacitor must be 1 nF ±20%. If sync-on-green

is not used, this connection is not required. The sync-on-green

signal is always negative polarity.

RIN

BIN

GIN

SOG

47nF

1nF

Figure 5. Typical Clamp Configuration

CLOCK GENERATION

A phase-locked loop (PLL) is used to generate the pixel clock.

In this PLL, the Hsync input provides a reference frequency. A

voltage controlled oscillator (VCO) generates a much higher

pixel clock frequency. This pixel clock is divided by the PLL

divide value (Register 0x01 and Register 0x02) and phase

compared with the Hsync input. Any error is used to shift the

VCO frequency and maintain lock between the two signals.

The stability of this clock is a very important element in provid-

ing the clearest and most stable image. During each pixel time,

there is a period during which the signal is slewing from the old

pixel amplitude and settling at its new value. Then, there is a

time when the input voltage is stable before the signal must slew

to a new value (Figure 6). The ratio of the slewing time to the

stable time is a function of the bandwidth of the graphics DAC

and the bandwidth of the transmission system (cable and

termination). It is also a function of the overall pixel rate.

Clearly, if the dynamic characteristics of the system remain

fixed, the slewing and settling time is, likewise, fixed. This time

must be subtracted from the total pixel period, leaving the

stable period. At higher pixel frequencies, the total cycle time is

shorter, and the stable pixel time also becomes shorter.

PIXEL CLOCK

INVALID SAMPLE TIMES

Figure 6. Pixel Sampling Times

Any jitter in the clock reduces the precision with which the

sampling time can be determined, and must also be subtracted

from the stable pixel time.

Considerable care has been taken in the design of the

AD9985A’s clock generation circuit to minimize jitter. As shown

in Figure 7, the clock jitter of the AD9985A is less than 5% of

the total pixel time in all operating modes, making the

reduction in the valid sampling time negligible due to jitter.

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