 |
Moteur de recherche de fiches techniques de composants électroniques |
|
|
Moteur de recherche de fiches techniques de composants électroniques |
|
AD9985A/PCB Fiches technique(PDF) 15 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
AD9985A/PCB Fiches technique(HTML) 15 Page - Analog Devices |
|
|
15 / 32 page  AD9985A Rev. 0 | Page 15 of 32 Table 9. Recommended VCO Range and Charge Pump Current Settings for Standard Display Formats Standard Modes Resolution Refresh Rate Horizontal Frequency Pixel Rate PLL Div AD9985AKSTZ VCORNGE Current AD9985ABSTZ VCORNGE Current VGA 640 × 480 60 Hz 31.5 kHz 25.175 MHz 799 00 110 00 011 72 Hz 37.7 kHz 31.500 MHz 835 00 110 01 010 75 Hz 37.5 kHz 31.500 MHz 841 00 110 01 010 85 Hz 43.3 kHz 36.000 MHz 831 01 100 01 010 SVGA 800 × 600 56 Hz 35.1 kHz 36.000 MHz 1025 01 100 01 010 60 Hz 37.9 kHz 40.000 MHz 1055 01 100 01 011 72 Hz 48.1 kHz 50.000 MHz 1039 01 101 01 100 75 Hz 46.9 kHz 49.500 MHz 1055 01 101 01 100 85 Hz 53.7 kHz 56.250 MHz 1047 01 101 01 101 XGA 1024 × 768 60 Hz 48.4 kHz 65.000 MHz 1343 10 101 10 011 70 Hz 56.5 kHz 75.000 MHz 1327 10 100 10 011 75 Hz 60.0 kHz 78.750 MHz 1313 10 100 10 011 80 Hz 64.0 kHz 85.500 MHz 1335 10 101 10 100 85 Hz 68.3 kHz 94.500 MHz 1383 10 101 10 100 SXGA 1280 × 1024 60 Hz 64.0 kHz 108.000 MHz 1687 10 110 10 101 75 Hz 80.0 kHz 135.000 MHz 1687 11 110 TV Modes 480i 720 × 480 60Hz 15.75 kHz 13.51MHz 857 00 011 00 011 480p 720 × 483 60Hz 31.47 kHz 27.00 MHz 857 00 110 00 011 720p 1280 × 720 60Hz 45.0 kHz 74.25 MHz 1649 10 100 10 011 1080i 1920 × 1080 60Hz 33.75 kHz 74.25 MHz 2199 10 100 10 011 TIMING The timing diagrams in this section show the operation of the AD9985A. The output data clock signal is created so that its rising edge always occurs between data transitions, and can be used to latch the output data externally. The pipeline in the AD9985A must be flushed before valid data becomes available. This means that four data sets are presented before valid data is available. tPER tCYCLE tSKEW DATACK DATA HSOUT Figure 9. Output Timing Hsync TIMING Hsync is processed in the AD9985A to eliminate ambiguity in the timing of the leading edge with respect to the phase-delayed pixel clock and data. The Hsync input is used as a reference to generate the pixel sampling clock. The sampling phase can be adjusted, with respect to Hsync, through a full 360° in 32 steps via the phase adjust register (to optimize the pixel sampling time). Display systems use Hsync to align memory and display write cycles; therefore, it is important to have a stable timing relationship between Hsync output (HSOUT) and data clock (DATACK). Three things happen to Horizontal Sync in the AD9985A. First, the polarity of Hsync input is determined and thus has a known output polarity. The known output polarity can be programmed either active high or active low (Register 0x0E, Bit 5). Second, HSOUT is aligned with DATACK and data outputs. Third, the duration of HSOUT (in pixel clocks) is set via Register 0x07. HSOUT is the sync signal that should be used to drive the rest of the display system. |
|
Lien URL |
| ALLDATASHEET vous a-t-il été utile ? [ DONATE ] |
À propos de Alldatasheet | Publicité | Contactez-nous | Politique de confidentialité | Lien vers la fiche technique | Echange de liens | Fabricants All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
French ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
