AD9985ASLASHPCB datasheet(14/32 Pages) AD

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AD9985A

Rev. 0 | Page 14 of 32

FREQUENCY (MHz)

10 20 30 40 50 60 70 80 90 100 110 120 130 140 150

Figure 7. Pixel Clock Jitter vs. Frequency

The PLL characteristics are determined by the loop filter design,

the PLL charge pump current, and the VCO range setting. The

loop filter design is shown in Figure 8. Recommended settings

of VCO range and charge pump current for VESA standard

display modes are listed in Table 9.

0.0082

μF

0.082

μF

2.7k

FILT

PVD

Figure 8. PLL Loop Filter Detail

Four programmable registers are provided to optimize the

performance of the PLL.

12-Bit Divisor Register

The input Hsync frequencies range from 15 kHz to 110 kHz.

The PLL multiplies the frequency of the Hsync signal,

producing pixel clock frequencies in the range of 12 MHz to

110 MHz. The divisor register controls the exact multiplication

factor. This register can be set to any value between 221 and

4095. (The divide ratio that is actually used is the programmed

divide ratio plus 1.)

2-Bit VCO Range Register

To improve the noise performance of the AD9985A, the VCO

operating frequency range is divided into three overlapping

regions. The VCO range register sets this operating range.

Table 6 shows the frequency ranges for the lowest and highest

regions.

Table 6. VCO Frequency Ranges

Pixel Clock Range (MHz)

PV1

PV0

AD9985AKSTZ

AD9985ABSTZ

12 to 32

12 to 30

32 to 64

30 to 60

64 to 110

60 to 110

110 to 140

3-Bit Charge Pump Current Register

This register allows the current that drives the low-pass loop filter

to be varied. The possible current values are listed in Table 7.

Table 7. Charge Pump Current/Control Bits

Ip2

Ip1

Ip0

Current (μA)

100

150

250

350

500

750

1500

5-Bit Phase Adjust Register

The phase of the generated sampling clock can be shifted to

locate an optimum sampling point within a clock cycle. The

phase adjust register provides 32 phase-shift steps of 11.25°

each. The Hsync signal with an identical phase shift is available

through the HSOUT pin.

The COAST pin is used to allow the PLL to continue to run at

the same frequency in the absence of the incoming Hsync signal

or during disturbances in Hsync (such as equalization pulses).

This can be used during the vertical sync period, or any other

time that the Hsync signal is unavailable. The polarity of the

Coast signal is set through the Coast polarity register. Also, the

polarity of the Hsync signal is set through the Hsync polarity

and Coast polarity bits should be set to match the respective

polarities of the input signals.

POWER MANAGEMENT

The AD9985A uses the activity detect circuits, the active

interface bits in the serial bus, the active interface override bits,

and the power-down bit to determine the correct power state.

The three power states are full-power, seek mode, and power-

down. Table 8 summarizes how the AD9985A determines

which power mode to be in and which circuitry is powered

on/off in each of these modes. The power-down command has

priority over the automatic circuitry.

Table 8. Power-Down Mode Descriptions

Mode

Inputs

Power-Down1

Sync

Detect2

Powered On or

Comments

Full-

Power

Everything

Seek

Mode

Serial Bus, Sync Activity

Detect, SOG, Band Gap

Reference

Power-

Down

Serial Bus, Sync Activity

Detect, SOG, Band Gap

Reference

1 Power-down is controlled via Bit 1 in Serial Bus Register 0x0F.

2 Sync detect is determined by OR’ing Bits 7, 4, and 1 in Serial Bus Register 0x14.

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