AD9985A

Rev. 0 | Page 17 of 32

2-WIRE SERIAL REGISTER MAP

The AD9985A is initialized and controlled by a set of registers that determine the operating modes. An external controller is used to write

and read the control registers through the two-line serial interface port.

Table 10. Control Register Map

Hexadecimal

Address

Write and

Read or

Read-Only

Bits

Default

Value

Register

Name

Function

0x00

RO

7:0

Chip Revision

An 8-bit register that represents the silicon revision level.

0x011

R/W

7:0

01101001

PLL Div MSB

This register is for Bits [11:4] of the PLL divider. Greater values mean

the PLL operates at a faster rate. This register should be loaded first

whenever a change is needed. This will give the PLL more time to lock.

0x021

R/W

7:4

1101****

PLL Div LSB

Bits [7:4] of this word are written to the LSBs [3:0] of the PLL divider

word.

0x03

R/W

7:3

01******

Bits [7:6] VCO Range. Selects VCO frequency range. (See the PLL

description.)

**001***

Bits [5:3] Charge Pump Current. Varies the current that drives the

low-pass filter. (See the PLL description.)

0x04

R/W

7:3

10000***

Phase Adjust

ADC Clock Phase Adjustment. Larger values mean more delay.

(1 LSB = T/32)

0x05

R/W

7:0

10000000

Clamp

Placement

Places the clamp signal an integer number of clock periods after the

trailing edge of the Hsync signal.

0x06

R/W

7:0

10000000

Clamp

Duration

Number of clock periods that the clamp signal is actively clamping.

0x07

R/W

7:0

00100000

Hsync Output

Pulse Width

Sets the number of pixel clocks that HSOUT will remain active.

0x08

R/W

7:0

10000000

Red Gain

0x09

R/W

7:0

10000000

Green Gain

0x0A

R/W

7:0

10000000

Blue Gain

Controls the ADC input range (contrast) of each respective channel.

Greater values give less contrast.

0x0B

R/W

7:1

1000000*

Red Offset

0x0C

R/W

7:1

1000000*

Green Offset

0x0D

R/W

7:1

1000000*

Blue Offset

Controls dc offset (brightness) of each respective channel. Greater

values decrease brightness.

0x0E

R/W

7:0

0*******

Sync Control

Bit 7—Hsync Polarity Override. (Logic 0 = polarity determined by

chip, Logic 1 = polarity set by Bit 6 in Register 0x0E.)

*1******

Bit 6—Hsync Input Polarity. Indicates polarity of incoming Hsync

signal to the PLL. (Logic 0 = active low, Logic 1 = active high.)

**0*****

Bit 5—Hsync Output Polarity. (Logic 0 = logic high sync,

Logic 1 = logic low sync.)

***0****

Bit 4—Active Hsync Override. If set to Logic 1, the user can select the

Hsync to be used via Bit 3. If set to Logic 0, the active interface is

selected via Bit 6 in Register 0x14.

****0***

Bit 3—Active Hsync Select. Logic 0 selects Hsync as the active sync.

Logic 1 selects sync-on-green as the active sync. Note that the

indicated Hsync is used only if Bit 4 is set to Logic 1 or if both syncs

are active. (Bits 1, 7 = Logic 1 in Register 0x14.)

*****0**

Bit 2—Vsync Output Invert. (Logic 1 = no invert, Logic 0 = invert.)

******0*

Bit 1—Active Vsync Override. If set to Logic 1, the user can select the

Vsync to be used via Bit 0. If set to Logic 0, the active interface is

selected via Bit 3 in Register 0x14.

*******0

Bit 0—Active Vsync Select. Logic 0 selects raw Vsync as the output

Vsync. Logic 1 selects sync separated Vsync as the output Vsync.

Note that the indicated Vsync is used only if Bit 1 is set to Logic 1.

0x0F

R/W

7:1

0*******

Bit 7—Clamp Function. Chooses between Hsync for clamp signal or

another external signal to be used for clamping. (Logic 0 = Hsync,

Logic 1 = Clamp.)