AD9985ASLASHPCB datasheet(20/32 Pages) AD

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AD9985A

Rev. 0 | Page 20 of 32

The power-up default value of PLLDIV is 1693

(PLLDIVM = 0x69, PLLDIVL = 0xDx). The

AD9985A updates the full divide ratio only when this

CLOCK GENERATOR CONTROL

7–6

VCO Range Select

Two bits that establish the operating range of the clock

generator.

VCORNGE must be set to correspond with the

desired operating frequency (incoming pixel rate).

The PLL gives the best jitter performance at high

frequencies. For this reason, to output low pixel rates

and still get good jitter performance, the PLL actually

operates at a higher frequency but then divides down

the clock rate afterwards. Table 11 shows the pixel

rates for each VCO range setting. The PLL output

divisor is automatically selected with the VCO range

setting.

Table 11. VCO Ranges

Pixel Clock Range (MHz)

PV1

PV0

AD9985AKSTZ

AD9985ABSTZ

12 to 32

12 to 30

32 to 64 (power-up

default)

30 to 60 (power-up

default)

64 to 110

60 to 110

110 to 140

5–3

Current Charge Pump Current

Three bits that establish the current driving the loop

filter in the clock generator.

Current must be set to correspond with the desired

operating frequency (incoming pixel rate).

Table 12. Charge Pump Currents

CURRENT

Current (μA)

000

001

100 (power-up default)

010

150

011

250

100

350

101

500

110

750

111

1500

7–3

Clock Phase Adjust

A 5-bit value that adjusts the sampling phase in 32

steps across one pixel time. Each step represents an

11.25° shift in sampling phase.

The power-up default value is 16.

CLAMP TIMING

7–0

Clamp Placement

An 8-bit register that sets the position of the internally

generated clamp.

When clamp function (Register 0x0F, Bit 7) = 0, a

clamp signal is generated internally, at a position

established by the clamp placement and for a duration

set by the clamp duration. Clamping is started (clamp

placement) pixel periods after the trailing edge of

Hsync. The clamp placement can be programmed to

any value between 1 and 255.

The clamp should be placed during a time that the

input signal presents a stable black-level reference,

usually the back porch period between Hsync and the

image.

When clamp function = 1, this register is ignored.

7–0

Clamp Duration

An 8-bit register that sets the duration of the

internally generated clamp.

For the best results, the clamp duration should be set

to include the majority of the black reference signal

time that follows the Hsync signal trailing edge.

Insufficient clamping time can produce brightness

changes at the top of the screen, and a slow recovery

from large changes in the average picture level (APL),

or brightness.

When clamp function = 1, this register is ignored.

HSYNC PULSE WIDTH

7–0

Hsync Output Pulse Width

An 8-bit register that sets the duration of the Hsync

output pulse.

The leading edge of the Hsync output is triggered by

the internally generated, phase-adjusted PLL feedback

clock. The AD9985A then counts a number of pixel

clocks equal to the value in this register. This triggers

the trailing edge of the Hsync output, which is also

phase adjusted.

INPUT GAIN

7–0

Red Channel Gain Adjust (REDGAIN)

An 8-bit word that sets the gain of the red channel.

The AD9985A can accommodate input signals with a

full-scale range of between 0.5 V and 1.0 V p-p.

Setting REDGAIN to 255 corresponds to a 1.0 V input

range. A REDGAIN of 0 establishes a 0.5 V input

range. Increasing REDGAIN results in the picture

having less contrast (the input signal uses fewer of the

available converter codes). See Figure 4.

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