STWBC2-HP datasheet(42/96 Pages) STMICROELECTRONICS

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2.2.5.3

Functional description

The IP generates the ADC selection lines interconnected to an eight-way analog multiplexer; this IP

is instantiated three times (one instance per ADC channel). The sel_in[2:0] lines are provided by the

ADC_MUX_<x>_ADC_MUX_<x> internal registers while the latch_en signal is interconnected with the register bit

ADC_MUX_<x>_LATCH_ADC<x>_EN. The trig signal is interconnected with the adc_mux_trig signal generated

by a GPIO signal; this command allows to pipeline the analog mux channel selection during fast ADC conversion.

When the channel selection is configured in latch mode, the Adc_mux_trig signal latches the mux selection lines.

The Adc_mux_trig comes from the STM32 GPIO signal. When using latch mode, the FW can prepare the next

mux selection by accessing the SPI registers while an ADC conversion is on-going. This selection is applied only

after the Adc_mux_trig GPIO toggling. In this way, the SPI access time can be pipelined in respect to the ADC

conversion improving the bandwidth conversion.

Note that “<x>” in the register name means that the bit field is replicated three times to be interconnected with all

instance modules.

Here below is shown the internal circuit block diagram:

Figure 44. ADC_MUX block diagram overview

2.2.5.4

Configuration register overview

Table 31 shows the list of ADC_MUX configuration registers overview:

Table 31. ADC_MUX configuration registers overview

Registers overview

Name

Description

Type

Page

Offset

Reset val.

ADC_MUX_0

Mux0 to ADC0

R/W

0x05

0x00

ADC_MUX_1

Mux1 to ADC1

R/W

0x06

0x00

ADC_MUX_2

Mux2 to ADC2

R/W

0x07

0x00

2.2.6

LED_SPK pattern generator

2.2.6.1

Overview

This block generates a configurable pattern output signal in the range of Hz for LED monitor or kHz for the buzzer

audio speaker.

2.2.6.2

Feature list

•

Programmable pulse pattern generator

•

Configurable parameters:

–

Pattern output data

–

Clock pre-scale

–

Clock pre-divider

–

Current sink

•

Control enable functionality

•

Two independent modules instantiated

•

Alternatively, I/O signal configuration

STWBC2-HP

Digital AFE functions

DS13825 - Rev 1.0

page 42/96

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