STWBC2-HP datasheet(29/96 Pages) STMICROELECTRONICS

29 / 96 page

The HR-PWM processes step incrementally from 0 to n (max. step number). The steps associated with an FSK

bit polarity different from the running FSK bit are ignored. In the steps that have no output toggling and no capture

toggling are ignored. However, it is possible to insert a step that has no output or capture toggling request if

FSK and FSKb bits of the step are both set to 1. Such a step can be considered as a simple delay step. When

reaching the end of the step list, the HR-PWM rolls over to step 0. By default, the end of the step list corresponds

to the first step programmed with no output toggling or capture window having FSK & FSKb at 1. It is possible

to force the HR-PWM to scan the entire list of steps (so from 0 to n) before rolling over. To do so, set the bit

SCAN_FULL_LIST in the PWM_CONTROL_2 register.

•

Sequencer enable:

–

At enabling, the HR-PWM applies an initial state coded in PWM_INITIAL_STATE register to the outputs

and capture window. By default, the next output and capture states depend on the toggling coded in

the different steps. It is however possible to force the application of PWM_INITIAL_STATE register to

the outputs and capture window at each list of step rollover. To do so, set the bit OUTPUT_REINIT in

the PWM_CONTROL_2 register.

•

Sequencer disable:

–

At disabling, the HR-PWM waits for list of step rollover and then engages a disabling procedure. The

steps in the list are processed normally except that only the toggling from 1 to 0 are applied to the

outputs and capture window. When all outputs are 0, the HR-PWM is effectively disabled. The state of

HR-PWM is monitored by the bit PWM_RUNNING in the PWM_STATUS register.

The enabling/disabling of HR-PWM is done using the bit ENABLE in the PWM_CONTROL_1 register. When

HR-PWM is running and ENABLE bit is written to 0, the disabling procedure is engaged. In this case, the

disabling time depends on the programming of steps. If an immediate disabling of HR-PWM is required, set the

bit FORCE_OFF in the PWM_CONTROL_2 register and wait for the bit PWM_RUNNING in the PWM_STATUS to

pass to 0. Then, clear the FORCE_OFF bit.

•

Pipeline configuration

–

The HR-PWM runs on a copy of steps registers and the PWM_INITIAL_STATE register. It is then

possible to write a new step configuration in registers without disrupting a running sequence. A copy

of steps registers and PWM_INITIAL_STATE register is done automatically when the HR-PWM is

enabled. A copy can also be triggered while HR-PWM is running to update the sequence. When

writing 1 in bit UPDATE_STEPS of the PWM_CONTROL_2 register, a copy is done at next rollover of

list of steps. This allows doing a synchronous update of the PWM generation. When writing 1 in bit

PUSH_STEPS of the PWM_CONTROL_2 register, the copy of registers is done immediately.

The basic configuration HR-PWM requires the following steps:

Configure the complementary mode of PWM0 & 1 (bit PWM_2_3_AS_COMPLEMENT)

Write the sequence of steps in the corresponding registers

Write the initial state of outputs (PWM_INITIAL_STATE)

Set the options of list processing (OUTPUT_REINIT bit and SCAN_FULL_LIST bit)

Enable the HR-PWM (ENABLE bit)

While running, a new sequence can be written in the registers. When registers write is done, update this new

sequence in the HR-PWM sequencer (UPDATE_STEPS bit or PUSH_STEPS bit).

The HR-PWM can be gracefully disabled by clearing the ENABLE bit. It will be effectively disabled when

PWM_RUNNING bit is 0. Alternatively, the HR-PWM can be immediately disabled using FORCE_OFF bit.

2.2.1.4.2

FSK configuration

The HR-PWM includes an FSK function that allows sending data to a WPC-Qi receiver using Frequency Shift

Keying messaging. The variation of PWM frequency is pre-programmed in the list of steps. In fact, the different

steps in the list can be associated to a polarity of the FSK signal. When the FSK polarity of a step is not the same

as the FSK signal in the HR-PWM, the step is simply ignored. Then, the list can include some steps associated

with a particular polarity of FSK. Depending on the running FSK signal polarity, the PWM timings are different

as some steps will be active or not. This can lead to different PWM frequencies depending on the state of FSK

signal.

For debug or verification, it is possible to force the FSK signal to 1 in a continuous way (by default FSK signal is

0). To do so, set the bit DBG_FSK in the PWM_CONTROL_2 register. This debug mode allows verifying that the

FSK enabled sequence is giving the expected result.

The WPC-Qi FSK consists of converting data bits in NRZ symbols. A data bit at 1 gives 2 opposite symbols (01 or

10), a data bit at 0 gives 2 similar symbols (00 or 11). Between each bit, the symbol polarity inverts.

STWBC2-HP

Digital AFE functions

DS13825 - Rev 1.0

page 29/96

STWBC2-HP Fiches technique(PDF) 29 Page - STMicroelectronics

STWBC2-HP Fiches technique(HTML) 29 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96

Fiches technique Télécharger

Lien URL