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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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STMPE812 Fiches technique(PDF) 19 Page - STMicroelectronics |
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STMPE812 Fiches technique(HTML) 19 Page - STMicroelectronics |
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19 / 51 page  STMPE812 Interrupt system Doc ID 17732 Rev 3 19/51 8 Interrupt system The STMPE812 uses a 2-tier interrupt structure. In normal mode, interrupts from the GPIO and touchscreen controller assert the INT pin and are available in the Interrupt Status register (ISR). In pen down mode, the INT pin is asserted as long as pen down is detected. Since the INT pin is a OR function of the pen down and all other enabled interrupts, in order for INT pin to provide the exclusive indication of pen down (INT=Low) and pen up (INT=High), as such benefit from minimal I2C transactions, it is recommended to use pen down mode when the GPIO/PWM/ADC functions are not required or the GPIO/PWM/ADC interrupts are disabled. Figure 7. Interrupt system diagram Obsolete Product(s) - Obsolete Product(s) |
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