M66273FP datasheet(9/34 Pages) MITSUBISHI

9 / 34 page

LCD CONTROLLER with VRAM

M66273FP

MITSUBISHI <DIGITAL ASSP>

Ver.3.1 Dec,1999

[R2] MPUI/LCD mode

R/W

Address

Function

Reset

WAITC

MCS and RD or H/LWR

control

WAITCNT control

·Set to select trigger signal of WAIT output.

·When setting WAITC to "0", change WAIT to "L" at timing of

falling edge of overlapping with MCS and RD or LWR and

HWR. And return to "H" at synchronization with the rising

edge of MPUCLK offer internal processing.

·When setting WAITC to "T", change WAIT to "L" at timing of

falling edge of WAITCNT on MCS="L".And return to "H" at

synchronization with rising edge of MPUCLK after internal

processing.

·Output WAIT only when requested access from MPU to

VRAM is gained during cycle steal access.

·Resetting set WAITC ="0".

Set the display data output mode on the LCD side.

Restriction

D7 , D6 are not used.

R/W

02H

·To read R2, "0" is output to D7 , D6.

SWAP

1 Order of lower/upper byte

Order of upper/lower byte

·When selecting 16 bit MPU, set SWAP to "0" to transfer

VD<n:0> in order of Upper/Lower byte of MPU data

bus,reversally set to "1" in order of Lower/Upper byte.

·When selecting 8 bit MPU, set to "0"

·Even if setting to "1", use D<7:0> to access to register of

8 bit width.

·Resetting set SWAP="0".

DUAL

1 screen driving panel

2 screen driving panel

·Set the LCD panel configuration.

·Resetting sets the 1 screen driving panel.

·Set the LCD display mode (binary or gray scale).

·Resetting sets the binary display mode.

GRAY

Binary display mode

Gray scale display mode

4/8

·Set the transfer path width of the LCD display data path

VD<n:0>.

·Resetting sets 4bit transfer.

4bit transfer

8bit transfer

·set when register is

initialized.

·set when register is

initialized.

·set when register is

initialized.

·set when register is

initialized.

·set when register is

initialized.

·When setting to

"0",connect

WAITCNT input to

VSS or VDD.

D3 is not used.

·To read R2, "0" is output to D3.

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