M66273FP datasheet(4/34 Pages) MITSUBISHI

4 / 34 page

LCD CONTROLLER with VRAM

M66273FP

MITSUBISHI <DIGITAL ASSP>

Ver.3.1 Dec,1999

PIN DESCRIPTIONS

N.C

No connection

VSS

Ground

VDD

Power supply pin

Pin name

Input/

Output

Function

Number

of pins

VD<7:0>

Display data bus for LCD

Transfer the LCD display data in synchronization with a rising edge of CP by putting 4-bit or 8-bit in

parallel.

The VD<n:0> output pin in use differs depending on the number of driven screens and the display

mode.

Display data transfer clock

Shift clock for the transfer of display data to LCD.

Take the display data of VD<n:0> to LCD at falling edge of CP.

Display data latch pulse

This clock use both as the latch pulse of display data for LCD and the transfer of scanning signal.

LP is output when it finishes transferring display data of a line.

Latch of display data and the transfer of scanning signal at falling edge of LP.

First Line Marker signal output

Output the start pulse of scanning line.

This signal is "H" active, the IC for driving scanning line catches FLM at falling edge of LP.

FLM

LCD alternating signal output

Signal for driving LCD by alternating current.

LCDENB

LCD (ON/OFF) control signal output

Output data which is set at bit "0" of mode register (R1) in the control register. This signal can be used

for controlling the LCD power supply, because LCDENB is set to "L" by RESET.

Item

LCD

interface

Others

Output

DIFFERENCE BETWEEN M66273FP AND M66272FP

The M66273FP is an adv anced product f rom the M66272FP at the point of MPU interf ace and timing

specif ications.

LCD display f unctions are the same with the M66272FP.

The f ollowing shows diff erence between the M66273FP and the M66272FP without timing specif ications.

Ref er to the later item about timing specif ications and detail specif ications.

It is capable of selecting WAIT output trigger input.

In case of fixed WAITCNT input, change WAIT to "L" at the

timing of the falling edge of overlapping with MCS and RD or

LWR/HWR, and in case of using WAITCNT input, change

WAIT to "L" at the timing of the falling edge of WAITCNT on

MCS="L".

Set by SWAP register.

WAITCNT input ( WAIT control input)

Pin f unction

WAIT output

control

Access to

control register

Specif ication

Bus swap f unction

M66273FP

M66272FP

SWAP input ( Bus swap input)

Set by SWAP pin.

Use IOCS pin for chip select of control register.

WAIT output change to "L" at the timing of the falling

edge of overlapping with MCS and RD or LWR/HWR.

Use IOCS or MCS pins for chip select of

control register.

(capable of controlling VRAM and control register by MCS

pin.)

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