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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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CS47L35 Fiches technique(PDF) 18 Page - Cirrus Logic |
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CS47L35 Fiches technique(HTML) 18 Page - Cirrus Logic |
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18 / 300 page  18 DS1085F3 CS47L35 3 Characteristics and Specifications Table 3-14. Digital Microphone (DMIC) Interface Timing The following timing information is valid across the full range of recommended operating conditions. Parameter 1 1.DMIC interface timing Symbol Minimum Typical Maximum Units DMICCLKn cycle time tCY 160 163 1432 ns DMICCLKn duty cycle — 45 — 55 % DMICCLKn rise/fall time (25-pF load, 1.8-V supply) tr, tf 5— 30 ns DMICDATn (Left) setup time to falling DMICCLK edge tLSU 15 — — ns DMICDATn (Left) hold time from falling DMICCLK edge tLH 0— — ns DMICDATn (Right) setup time to rising DMICCLK edge tRSU 15 — — ns DMICDATn (Right) hold time from rising DMICCLK edge tRH 0— — ns Note: The voltage reference for the IN1 and IN2 DMIC interfaces is selectable, using the INn_DMIC_SUP fields—each interface may be referenced to MICVDD, MICBIAS1B, MICBIAS2A, or MICBIAS2B levels. Table 3-15. Digital Speaker (PDM) Interface Timing The following timing information is valid across the full range of recommended operating conditions. Parameter Symbol Minimum Typical Maximum Units Mode A 1 1.Digital speaker (PDM) interface timing—Mode A SPKCLK cycle time tCY 160 163 358 ns SPKCLK duty cycle — 45 — 55 % SPKCLK rise/fall time (25-pF load) tr, tf 2— 8 ns SPKDAT set-up time to SPKCLK rising edge (left channel) tLSU 30 — — ns SPKDAT hold time from SPKCLK rising edge (left channel) tLH 30 — — ns SPKDAT set-up time to SPKCLK falling edge (right channel) tRSU 30 — — ns SPKDAT hold time from SPKCLK falling edge (right channel) tRH 30 — — ns Mode B 2 SPKCLK cycle time tCY 160 163 358 ns SPKCLK duty cycle — 45 — 55 % SPKCLK rise/fall time (25-pF load) tr, tf 2— 8 ns SPKDAT enable from SPKCLK rising edge (right channel) tREN — — 15 ns SPKDAT disable to SPKCLK falling edge (right channel) tRDIS —— 5 ns SPKDAT enable from SPKCLK falling edge (left channel) tLEN — — 15 ns SPKDAT disable to SPKCLK rising edge (left channel) tLDIS —— 5 ns (left data) (right data) DMICDAT (input) VIL VIH tRH tRSU tLH tLSU VOL DMICCLK (output) tCY VOH tr tf SPKCLK (output) SPKDAT (output) tCY tLH tRH tLSU tRSU (left data) (right data) VOH VOL V OL tr tf VOH |
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