L99LD20 datasheet(34/61 Pages) STMICROELECTRONICS

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SPI functional description

L99LD20

34/61

DS11366 Rev 3

PWMCLK_FAIL

When this bit is set, a PWM Clock Fail is detected.

This occurs FPWMCLK ≤ FPWMCLK_FAIL. In this case PWMCLK

signal is bypassed by an internal fall back PWM frequency

clock (having a frequency equal to FFALLBACK_CLK).

PWMCLK normal operation will be restored after a R&C

operation, when PWMCLK frequency

FPWMCLK > FPWMCLK_FAIL.

R/C

VSPI_FAIL

VSPI failure bit

0: VSPI (external SPI Supply) present

1: VSPI not present (VSPI voltage lower than VSPI_UV): device

goes to Limp Home Mode

16÷15

WD_STATUS

Watchdog status bit: see Table 23

WD_FAIL

Watchdog failure bit:

0: watchdog OK;

1: watchdog failure in Active mode

When this bit is set, the device goes in Limp Home Mode

R/C

VS_UV

VS undervoltage bit

0: VS > VS_UV;

1: VS

≤ V

S_UV

TOFF_MIN1

Minimum off-time operation for Buck1

0: Off-time

≥ tOFF_MIN_BUCK

1: Off-time < tOFF_MIN_BUCK

TOFF_MIN2

Minimum off-time operation for Buck2

0: Off-time

≥ tOFF_MIN_BUCK

1: Off-time < tOFF_MIN_BUCK

TOFF_MAX1

Maximum off-time operation for Buck1:

0: Off-time < tOFF_MAX_BUCK

1: Off-time

≥ tOFF_MAX_BUCK

TOFF_MAX2

Maximum off-time operation for Buck2:

0: Off-time < tOFF_MAX_BUCK

1: Off-time

≥ tOFF_MAX_BUCK

8÷6

000

Reserved

DIN_ST

Direct input status bit.

Filtered replica of logical level at DIN pin.

Filtering time is equal to tDIN_ST.

4÷1

0000

Unused

Parity Bit

ODD Parity Bit Check

Table 21. SR#2: Status Register 2 (continued)

Bit

Default

Name

Description

Access

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