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L99LD20 Fiches technique(PDF) 19 Page - STMicroelectronics |
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L99LD20 Fiches technique(HTML) 19 Page - STMicroelectronics |
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19 / 61 page ![]() DS11366 Rev 3 19/61 L99LD20 Functional description 60 registers are configured accordingly, one (or both) buck converter(s) are activated and directly controlled by DIN pin. The default configuration is set in order to allow direct driving only for buck1, whilst buck2 is turned off. In case of limp home function, the default conditions are applied. PWM control through DIN has to take into account the DIN filter time (tDIN_FT, 32 µs typical) on rising edge to properly set the desired duty cycle. Dimming with integrated PWM generator This function allows modifying the average current on the LEDs by means of a dedicated control register (see bits <23:14> and bits <13:4> on Table 13: CR#1: Control Register 1). This function must be activated setting the right mapping bits configuration inside the control register 3, and in particular, CR#3<15:14> for Buck1 and CR#3<13:12> for Buck2. To set duty cycle, a 10-bit number must be written in the corresponding register, resulting in a 1024 steps of resolution. The duty cycle is determined through the following equation: Where N is the 10-bit number. The PWM frequency is depending on the PWM_CLK input signal with the following equation: Where PWM_LF is the LEDs dimming frequency. If PWM signal fails, an error bit is reported in the STATUS register where PWMCLK fail is located. An internal fallback oscillator is enabled in order to provide a fixed PWM frequency clock signal (FFALLBACK_CLK), whilst no changes is applied on the duty cycle. Once the external PWM is available again and after a read & clear operation on Status Register 2, the internal clock is disabled and PWM operation continues with the external clock (see Figure 12). 3.3 Protections 3.3.1 Temperature warning The device integrates a temperature warning with two thresholds TW1 and TW2 in each buck’s mosfet. If the Tj of the buck mosfet1 or buck mosfet2 rises above TW1 or TW2, the status bit TWxy is set (x = 1 or x = 2, it stands for the buck1 or buck2, y = 1 or y = 2, it stands for the TW1 or TW2) . TWXY bit is set on the status registers: SR#1<4:3> for Buck1 and SR#2<22:21> for Buck2. Thermal warning is also reported in the Global Status Byte register, and in particular, bit 25 (GW) is set. If the Tj drops below the temperature warning reset threshold 1 (TW1-TW1_HYS), respectively TW2 – TW2_HYS, the corresponding status bit is automatically reset. As long as the Tj does not exceed the over temperature shutdown, the device does not latches off the buck mosfets, even if a temperature warning is detected. DC % N 1024 ------------- 100 ⋅ = PWM_LF PWM_CLK 1024 ----------------------------- = |
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