L6364 datasheet(40/60 Pages) STMICROELECTRONICS

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Linear regulators

In addition to the DC-DC regulator, the L6364 includes two 50 mA linear regulators supplied from the VDCDC pin,

which have internally set output levels at 3.3 V (V3V3 pin) and 5.0 V (V5V pin). The 3.3 V linear regulator acts as

the master, and the 5.0 V linear regulator as the slave.

The start-up time of the 5.0 V linear regulator is thus dependent on the 3.3 V level, and on the size of the 3.3 V

line capacitance, CV3V3. The regulators' dynamic start-up behaviour under different conditions of load capacitance

can be seen in Figure 17.

A typical load of 10mA, a supply voltage of 24 V with a rise time of 2.4 V/μs on pin VPLUS were used.

The core of the L6364 device is supplied by the V3V3 rail, and thus an external blocking capacitor CV3V3 for

stable operation is required and is mandatory. A maximum static load, equivalent to a resistor RSTART_MIN, may

be drawn externally on V3V3 during startup. A static load is the current which would be drawn continuously by the

application circuit if the output voltage, VSNS, were held at a fixed level. A load in excess of this level may block

the startup.

A higher dynamic load (eg. capacitor charging) is permitted. Dynamic loads affect (slow) the start, but do not block

startup.

In normal operation the consumption of the L6364 itself is limited to the quiescent current, IQUIES. During startup,

the static load contributed by the L6364 on the supply is limited to IQUIES_START. The actual load is increased by

the current drawn to charge the application capacitors and any external loads.

Figure 17. L6364 linear regulators' startup under different conditions of load capacitance

3.3V Linear Regulator Startup, Load = 10mA, Temp = 27°C

5.0V Linear Regulator Startup, Load = 10mA, Temp = 27°C

The 5.0 V regulator output is not used internally and is provided for external use. When in use, an external

blocking capacitor CV5V must be provided for stable operation, and the input supply range must be sufficient

(VVPLUS > VSUP in pure mode or VDCDC > VDCDC_5V_MIN for DC-DC operation).

When the 5.0 V linear regulator is not in use, either permanently or periodically, then this block may be placed in a

power-down state by setting bit CFG:PD5V.

When this bit is set to '1', the 5.0 V regulator is placed in power-down and the output pin, V5V, is pulled low with a

discharge current of IPD5V.

This ensures capacitances on the line are discharged cleanly, and that the output is tied to a known state.

L6364

Linear regulators

DS13363 - Rev 4

page 40/60

L6364 Fiches technique(PDF) 40 Page - STMicroelectronics