L6364 datasheet(19/60 Pages) STMICROELECTRONICS

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8.1.10

SPI register writes outside interrupt service routines

The interrupt service routine typically accesses the SPI, and so it is necessary to avoid a collision between an

interrupt service routine SPI access and any other SPI access made from the microcontroller.

Accessing the SPI clears a short-circuit or overtemperature interrupt, and so the received value of these bits must

be recorded by the microcontroller.

If a function makes a number of sequential SPI accesses, then it is reasonable to ignore these status bits on all

but the last access, and record the values read on this last access.

It is not necessary to check the STATUS:DAT bit outside the interrupt service routine, since the data interrupt

remains active until the microcontroller responds.

8.2

Single octet UART mode

The L6364 supports an operating mode called Single octet UART mode, which performs a simplified data transfer

function, transferring one octet at a time in either direction.

In this mode, M-sequence type recognition (MSEQ:M2CNT), the number of on-demand data octets (MSEQ:OD1,

MSEQ:OD2) and checksum verification/generation are disabled and, therefore, must be realized by the

microcontroller.

Note, that an exchange is always triggered by the master. It is not possible to transmit data without first receiving

valid data. Figure 8 shows the single octet UART mode state machine. When the CCTL:SGL bit is set by the

microcontroller, the L6364 is set to single octet UART mode.

8.2.1

Buffering

The FR0 register and the L6364 UART internal register together provide double buffering of data in receive and

single buffering in transmit. In order to avoid buffer over- or under-runs it is necessary for the microcontroller to:

•

read FR0 before the UART writes a new octet in Receive mode (delay ca. 11xTBIT), or

•

write FR0 before the UART requires a new octet in Transmit mode (delay ca. 3xTBIT).

8.2.2

Receive mode

In Receive mode the L6364 has the following states:

•

Receive wait:

The L6364 has received a complete master octet via the CQ channel. A data interrupt is generated

(STATUS:DAT='1') and the received octet is placed in the FR0 register.

The microcontroller has access to the FR0 register and reads the received octet. The state changes to

Receive Interim.

The UART continues to run in this state receiving the following frame. A buffer over-run results if the

microcontroller does not read FR0 before the frame completes. A UART frame is 11 bits, which at

230.4kBaud gives a period of 47μs for the two SPI accesses, each of 16 bits. At 4 MHz SPI this corresponds

to an SPI delay of 4 μs.

Error conditions: parity error, stop bit, time-out (more than 4xTBIT waiting for the next UART frame on

the CQ line), or buffer under-run are signaled with a data interrupt (STATUS:DAT='1') with additionally

STATUS:CHK='1'. The microcontroller should respond by writing LINK:END and discarding any received

octets.

The master stops sending after the last master octet and so a time-out is generally detected by the L6364

in the delay while the microcontroller is preparing the response. The condition is held internally in the L6364

and discarded by the L6364 when FR0 is written by the microcontroller, initiating transmission. The timeout

is therefore not reported to the microcontroller in this case.

•

Receive interim:

The UART receives data on the CQ line and copies this to the FR0 register, switching to Receive wait on

completion.

Once the expected number of octets is received, the microcontroller initiates sending by writing the first octet in

the response M-sequence to FR0, thereby switching the L6364 to Transmit mode (see Section 8.2.3 ). (In single

octet UART mode the equivalent of a LINK:SND command is achieved by writing to FR0).

L6364

Single octet UART mode

DS13363 - Rev 4

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