L6364 datasheet(36/60 Pages) STMICROELECTRONICS

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DC-DC converter

17.1

Converter configuration

The L6364 includes a DC-DC buck converter, which operates at a frequency configured by register

DCDC:FSET[2:0], shown in Table 30. Irregular frequency steps have been carefully chosen so to avoid simple

fractional multiples, such that it is possible to choose a controller frequency which does not interfere with a given

sensor frequency.

Table 30. DC-DC converter nominal operating frequency, FSET

DCDC:FSET

Frequency

DCDC:FSET

Frequency

[kHz]

500

1000

625

1250

710

1670

830

2000

The output voltage on pin VDCDC is configured by DCDC:VSET[2:0], shown in Table 31. Note that where

operation of the 5.0V linear regulator is required, the VDCDC output voltage must be configured to be at least

VDCDC_5V_MIN.

Table 31. DC-DC output voltage, VSET

DCDC:VSET

Target output

DCDC:VSET

target output

[V]

5.0

7.8

5.6

5(1)

8.6

6.1

9.6

6.8

10.5

1. Default value following reset.

Changes to the output voltage via VSET are executed in steps, with a delay of tVSET for each step between

VSETMIN and VSETMAX. This minimizes any over- or undershoot on VDCDC as the output voltage approaches the

target value. This implies that a maximum delay of ΔtVSET can occur between this range. If the DC-DC converter

is not required, the pin DOUT is externally shorted to pin VDCDC.

17.2

Converter architecture

The buck converter consists of two internal MOS switches (PMOS and NMOS), an external capacitor, CDCDC, and

an inductor LDCDC. The switches operate in anti-phase and, assuming no resistive losses, the output voltage on

VDCDCpin is equal to the duty ratio of the high-side switch multiplied by the input voltage (VVPLUS- VDIODE).

L6364

DC-DC converter

DS13363 - Rev 4

page 36/60

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