SH7041A datasheet(609/923 Pages) RENESAS

609 / 923 page

571

16.2

16.2.1

A/D Data Register A–D (ADDRA0–ADDRD0, ADDRA1–ADDRD1)

A/D registers are special registers that read stored results of A/D conversion in 16 bits. There are

eight registers: ADDRA0–ADDRD0 (A/D0) and ADDRA1–ADDRD1 (A/D1).

The A/D converted data is 10 bit data which is to the ADDR of the corresponding converted

channel for storage. The upper 8 bits of the A/D converted data correspond to the upper byte of the

ADDR and the lower 2 bits correspond to the lower byte. Bits 5–0 of the lower byte of ADDR are

reserved and always read 0. Analog input channels and correspondence to ADDR are shown in

table 16.3.

ADDR can always be read from the CPU. The upper byte may be read directly. The lower byte is

transferred through the temporary register (TEMP). For details, see section 16.3, Interface with

CPU.

ADDR is initialized to H'0000 during power-on reset or standby mode. ADDR will not be

initialized by manual reset.

AD9

AD8

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

—

0000000000000000

ADDRn :

R/W :

RRRRRRRRRRRRRRR

(n=A to D)

Initial value :

Bit :

Table 16.3

Analog Input Channel and ADDRA–ADDRD Correspondence

Analog Input Channel

A/D Data Register

Module

AN0

ADDRA0

A/D0

AN1

ADDRB0

AN2

ADDRC0

AN3

ADDRD0

AN4

ADDRA1

A/D1

AN5

ADDRB1

AN6

ADDRC1

AN7

ADDRD1

SH7041A Fiches technique(PDF) 609 Page - Renesas Technology Corp

SH7041A Fiches technique(HTML) 609 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Fiches technique Télécharger

Lien URL