SH7041A datasheet(559/923 Pages) RENESAS

No de pièce	SH7041A

Description	Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

PDF	923 Pages

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Fabricant	RENESAS [Renesas Technology Corp]

Site Internet	http://www.renesas.com

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521

RDRF

MPIE

RDR

value

ID1

ID2

MPB

Serial

data

Start

bit

Data

(ID2)

Data

(data 2)

Stop

bit

Start

bit

Stop

bit

Idling

(marking)

RxI interrupt request

(multiprocessor

interrupt), MPIE = 0

RxI interrupt handler

reads data in RDR

and clears RDRF to 0

Station’s ID, so receiving

continues, with data

received by the RxI

interrupt processing routine

MPIE

bit is again

set to 1

MPB

Data2

Example: Own ID matches data, 8-bit data with multiprocessor bit and one stop bit

Figure 14.15 Example of SCI Receive Operation (ID Matches)

14.3.4

Clock Synchronous Operation

In the clock synchronous mode, the SCI transmits and receives data in synchronization with clock

pulses. This mode is suitable for high-speed serial communication.

The SCI transmitter and receiver are independent, so full duplex communication is possible while

sharing the same clock. The transmitter and receiver are also double buffered, so continuous

transmitting or receiving is possible by reading or writing data while transmitting or receiving is in

progress.

Figure 14.16 shows the general format in clock synchronous serial communication.

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