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FXLS8967AF Fiches technique(PDF) 73 Page - NXP Semiconductors |
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FXLS8967AF Fiches technique(HTML) 73 Page - NXP Semiconductors |
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73 / 98 page ![]() NXP Semiconductors FXLS8967AF 3-Axis Low-g Accelerometer Field Description 4 Y_OT_EN SDCD function Y-axis outside-of-thresholds condition 0: Y-axis data or delta is not used in the outside of thresholds condition evaluation. 1: Y-axis data or delta is used in the outside of thresholds condition evaluation. 3 Z_OT_EN SDCD function Z-axis outside-of-thresholds condition 0: Z-axis data or delta is not used in the outside of thresholds condition evaluation. 1: Z-axis data or delta is used in the outside of thresholds condition evaluation. 2 X_WT_EN SDCD function X-axis within-thresholds condition 0: X-axis data or delta is not used in the within thresholds condition evaluation. 1: X-axis data or delta is used in the within thresholds condition evaluation. 1 Y_WT_EN SDCD function Y-axis within-thresholds condition 0: Y-axis data or delta is not used in the within thresholds condition evaluation. 1: Y-axis data or delta is used in the within thresholds condition evaluation. 0 Z_WT_EN SDCD function Z-axis within-thresholds condition 0: Z-axis data or delta is not used in the within thresholds condition evaluation. 1: Z-axis data or delta is used in the within thresholds condition evaluation. Table 101. SDCD_CONFIG1 register (address 2Fh) bit description...continued 15.31.4 SDCD_CONFIG2 register (address 30h) Bit 7 6 5 4 3 2 1 0 Name SDCD_EN REF_UPDM[1:0] OT_ DBCTM WT_ DBCTM WT_ LOG_SEL MODE REF_UPD Reset (BT_MODE = GND) 0 0 0 0 0 0 0 0 Reset (BT_MODE = VDD) 1 1 0 1 1 0 0 0 Access R/W R/W R/W R/W R/W R/W R/W R/W Table 102. SDCD_CONFIG2 register (address 30h) bit allocation Field Description 7 SDCD_EN SDCD function 0 (default after a POR or soft reset event when BT_MODE = GND): SDCD function is disabled. All clocks and power for the function are turned off. 1 (default after a POR or soft reset event when BT_MODE = VDD and MOT_DET = 1): SDCD function is enabled. When this bit is set, the 12-bit reference values ( REF_X/Y/Z) are initialized per the settings made in REF_UPDM[1:0]. Table 103. SDCD_CONFIG2 register (address 30h) bit description FXLS8967AF All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Objective data sheet Rev. 1 — 27 April 2021 73 / 98 |
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