FXLS8967AF datasheet(44/98 Pages) NXP

44 / 98 page

NXP Semiconductors

FXLS8967AF

3-Axis Low-g Accelerometer

Field

Description

RST

The RST bit may be used to initiate a software reset. The reset mechanism can be triggered in

Standby, Active (WAKE or SLEEP), and EXT_TRIG operating modes. When the RST bit is set, the

boot mechanism resets all functional blocks and loads the internal registers with their default values

(The

INT_POL, INT_PP_OD, and BOOT_DIS bits are not reset and maintains their current values

as long as power is not removed from the VDD pin and Hibernate mode is not enabled). The host

application should allow TBOOT1 or TBOOT2 ms between issuing a reset command and attempting

communications with FXLS8967AF over the I2C/SPI interfaces. Alternatively, the host can wait for the

active edge on the TBOOT1/2 pulse event signaled on the configured INTx pin.

0: No device reset pending

1: Write '1' to trigger the soft reset sequence

Notes:

• The I2C and SPI interface blocks are also reset to avoid corrupted data transactions.

• The reset sequence does not start until the host I2C controller issues the SP (stop) condition, or the

SPI primary releases the SPI_CS_B pin.

• The host always reads back this bit as '0'.

• There is a delay of 300 μs to 500 μs between setting the RST bit and the commencement of the

reset sequence.

6 to 5

ST_AXIS_SEL[1:0]

Self-test axis selection

This bit field selects the transducer axis to test using the Self-Test function. The ST_POL bit allows

either positive or negative self-test displacements to be applied.

The host system may use the self-test function to verify the functionality of both the transducer and

signal measurement chain without the need to apply an external acceleration stimulus.

Notes:

• The data output from the two axes that are not selected by ST_AXIS_SEL during the self-test

sequence are not meaningful and should be ignored.

• NXP recommends minimizing the communication traffic on the device serial interface during the

measurement phase in order to reduce the susceptibility of the self-test response signal to induced

noise. NXP strongly recommends operating the self-test in interrupt mode.

00b: (default): Self-test function is disabled

01b: Self-test function is enabled for X-axis

10b: Self-test function is enabled for Y-axis

11b: Self-test function is enabled for Z-axis

ST_POL

Self-test displacement polarity

0 (default): Proof mass displacement for the selected axis is in the positive direction.

1: Proof mass displacement for the selected axis is in the negative direction.

SPI_M

SPI interface mode selection; selects between 3- and 4-wire operating modes for the SPI interface:

0 (default): 4-wire interface mode is selected

1: 3-wire interface mode is selected

Notes:

• The state of this bit is only relevant when the SPI interface mode is selected (INTF_SEL = VDD).

• When INTF_SEL = VDD and SPI_M = 1, the SDA/SPI_MOSI pin becomes the bidirectional

SPI_DATA pin; the SA0/MISO pin is unused and placed in a high-impedance state.

• 4-wire mode is selected by default after a POR/BOR event or when exiting Hibernate mode.

• If INTF_SEL = VDD and the SPI_MOSI and SPI_MISO lines are directly connected together on the

PCB, 3-wire SPI mode is enabled regardless of the setting of this bit

Table 48. SENS_CONFIG1 register (address 15h) bit description

FXLS8967AF

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 27 April 2021

44 / 98

FXLS8967AF Fiches technique(PDF) 44 Page - NXP Semiconductors

FXLS8967AF Fiches technique(HTML) 44 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98

Fiches technique Télécharger

Lien URL