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CS7654 Fiches technique(PDF) 3 Page - Cirrus Logic |
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CS7654 Fiches technique(HTML) 3 Page - Cirrus Logic |
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3 / 62 page ![]() CS7654 3 INTERNAL REGISTER STRUCTURE AND USER INTERFACE ..................... 25 Operating CS7654 in Normal I2C Configuration (Three-Byte Mode) ....... 25 Station Address .................................................................................. 25 Write Operations in Three-Byte Mode ............................................... 25 Address Set Operation ....................................................................... 26 Read Operations in Three-Byte Mode ............................................... 26 Operating CS7654 in Four-Byte I2C Configuration ............................ 26 Write Operations in Four-Byte mode ................................................. 26 Read Operations in Four-Byte Mode ................................................. 27 Initializing Slave Devices on Secondary I2C bus from an EPROM .......... 27 Controlling the Configuration Process ...................................................... 28 Reserved Registers and Test Pins ........................................................... 29 General Purpose I/O Port ......................................................................... 29 ANALOG ............................................................................................................ 30 Analog Timing .......................................................................................... 30 VREF ........................................................................................................ 30 ISET-DAC ................................................................................................. 30 DACs ........................................................................................................ 30 Luminance DAC ................................................................................. 30 Chrominance DAC ............................................................................. 31 COMP_VID DAC ................................................................................ 31 REGISTER DESCRIPTION ............................................................................... 32 BOARD DESIGN AND LAYOUT CONSIDERATIONS ..................................... 53 Power and Ground Planes ....................................................................... 53 Power Supply Decoupling ........................................................................ 53 Digital Interconnect ................................................................................... 53 Analog Interconnect ................................................................................. 53 Analog Output Protection ......................................................................... 54 ESD and Latch up Protection ................................................................... 54 External DAC Output Filter ....................................................................... 54 PIN DESCRIPTIONS ......................................................................................... 55 PACKAGE DIMENSIONS ................................................................................. 60 |
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