CS7654 datasheet(58/62 Pages) CIRRUS

58 / 62 page

CS7654

CLKOUT - Digital Output Data Clock, PIN 29.

Digital output clock. Output data transitions on the falling edge of CLKOUT and can be

latched on the rising edge. The CLKOUT rate is equal to twice the input mosaic pixel rate

multiplied by the current scaling ratio with Y and CrCb output data available on DOUT [9:0].

Analog

VREF - External voltage reference, PIN 51.

Input to an external voltage reference of 1.235V. Leave floating if unused.

ISET_DAC - DAC bias, PIN 52.

Connect this pin to analog ground ( AGND ) through a 4K00 Ohms 1% resistor.

ISET_PLL - PLL bias, PIN 63.

Connect this pin to analog ground ( AGND ) through a 6K00 Ohms 1% resistor.

SVID_Y - S-Video output, LUMA , PIN 57.

Current DAC output, must have a doubly terminated load of 75R0 Ohms 1% resistor.

SVID_C - S-Video output, CHROMA , PIN 56.

Current DAC output, must have a doubly terminated load of 75R0 Ohms 1% resistor.

COMP_VID - Composite video output, PIN 53.

Current DAC output, must have a doubly terminated load of 75R0 Ohms 1% resistor.

Miscellaneous

RESET - Master External Reset Control, PIN 41.

CMOS input which initiates a complete power-on reset, where all registers are reset to their

defaults, and the secondary I2C bus attempts to load any EPROM configuration information.

This pin operates in conjunction with bit 0 of register 00h. RESET is an active logic low input.

TEST2 - Test Pin, PIN 42.

Test pin, connect to DGND.

TEST1 - Test Pin, PIN 64.

Test pin, connect to DGND.

SCENABLE - Test Pin, PIN 45.

Test pin, connect to GND.

CS7654 Fiches technique(PDF) 58 Page - Cirrus Logic