CS7654 datasheet(12/62 Pages) CIRRUS

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CS7654

CLKIN2X Input Timing

The CLKIN2X, pin 59, will always require a pri-

mary pixel rate clock source. CCD manufacturers

generally specify a pixel clock frequency that is

compatible with one of the analog encoders that

can be used with a given imager. If the analog out-

put is used, the clock frequency input must be

matched precisely. However, digital display sys-

tems, such as those based on VGA graphics adapter

cards and Zoom Video systems, are generally not

sensitive to pixel clock frequency, and will tolerate

a wide range of pixel and frame rates.

Specific pixel-rate clock frequencies for analog en-

coders include 14.31818 MHz for 768H imagers,

the primary ITU-601 13.5 MHz for 720H imagers,

and down to 12.272727 MHz clock rates for 640H

VGA format imagers.

CLKOUT_GRG

CLKOUT_GRG follows the output data rate The

clock output is at 2x the output luma sample rate,

there is no non-interlaced digital output on the

CS7654.

Mode

CCD Format

CCD Clock (MHz)

Output Format

Input Clock (MHz)

Scaling Ratio

000

CCD

½ input clock

same as CCD

(30 MHz max.)

1:1

001

512x480

9.818

640x480

24.5454

4:5

010

512x480

9.346

720x480

27.000

9:13

011

512x576

9.281

720x480

27.000

11:16

100

362x480

6.75

640x480

24.5454

11:20

101

362x480

6.75

720x480

27.000

1:2

362x576

6.75

720x576

27.000

110

512x576

9.563

720x576

27.000

17:24

111

512x480

9.000

720x480

27.000

2:3

512x576

9.000

720x576

27.000

Table 2. Default Scaling Modes (Register 04h at SA34h)

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