STMPE812A datasheet(8/53 Pages) STMICROELECTRONICS

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I2C interface

STMPE812A

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Doc ID 18225 Rev 4

I2C interface

For the bus master to communicate to the slave device, the bus master must initiate a Start

condition and be followed by the slave device address. Accompanying the slave device

address, there is a read/write bit (R/W). The bit is set to 1 for read and 0 for write operation.

If a match occurs on the slave device address, the corresponding device gives an

acknowledge on the SDA during the 9th bit time. If there is no match, it deselects itself from

the bus by not responding to the transaction.

Figure 4.

I2C timing diagram

Table 3.

I2C timing

Symbol

Parameter

Min

Typ

Max

Unit

fSCL

SCL clock frequency

400

kHz

tLOW

Clock low period

1.3

µs

tHIGH

Clock high period

600

SDA and SCL fall time

Note(1)

Minimum TF is subject to system capacitive load (CLOAD) condition.

300

tHD:STA

START condition hold time (after this

period the first clock is generated)

600

tSU:STA

START condition setup time (only relevant

for a repeated start period)

600

tSU:DAT

Data setup time

100

tHD:DAT

Data hold time

µs

tSU:STO

STOP condition setup time

600

tBUF

Time the bus must be free before a new

transmission can start

1.3

µs

AI00589

SDA

tSU:STO

tSU:STA

tHD:STA

SCL

tSU:DAT

tHD:DAT

tHIGH

tLOW

tHD:STA

tBUF

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