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STM32F070F6 Fiches technique(PDF) 54 Page - STMicroelectronics |
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STM32F070F6 Fiches technique(HTML) 54 Page - STMicroelectronics |
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54 / 83 page ![]() Electrical characteristics STM32F070CB/RB/C6/F6 54/83 DocID027114 Rev 3 Static latch-up Two complementary static tests are required on six parts to assess the latch-up performance: • A supply overvoltage is applied to each power supply pin. • A current injection is applied to each input, output and configurable I/O pin. These tests are compliant with EIA/JESD 78A IC latch-up standard. 6.3.13 I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below VSS or above VDDIOx (for standard, 3.3 V-capable I/O pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization. Functional susceptibility to I/O current injection While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures. The failure is indicated by an out of range parameter: ADC error above a certain limit (higher than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of the -5 µA/+0 µA range) or other functional failure (for example reset occurrence or oscillator frequency deviation). The characterization results are given in Table 44. Negative induced leakage current is caused by negative injection and positive induced leakage current is caused by positive injection. Table 42. ESD absolute maximum ratings Symbol Ratings Conditions Packages Class Maximum value(1) Unit VESD(HBM) Electrostatic discharge voltage (human body model) TA = +25 °C, conforming to JESD22-A114 All 2 2000 V VESD(CDM) Electrostatic discharge voltage (charge device model) TA = +25 °C, conforming to ANSI/ESD STM5.3.1 All C4 500 V 1. Data based on characterization results, not tested in production. Table 43. Electrical sensitivities Symbol Parameter Conditions Class LU Static latch-up class TA = +105 °C conforming to JESD78A II level A |
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