CS89712 datasheet(21/170 Pages) CIRRUS

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CS89712

DS502PP2

instructions immediately after the write to the

SNOOZE register location.

2.8.1.5

Doze State

Since Doze State can be considered a preliminary

state between Snooze State and Operating State,

the only requirement for existing this state into the

Operating State is for a few instructions to be exe-

cuted. Therefore, the latency is based solely upon

the time required to execute these instructions.

Table 10 summarizes the five external interrupt

sources and their effect on the processor interrupts.

2.9 Boot ROM

The 128 bytes of on-chip Boot ROM contain an in-

struction sequence that initializes the device and

then configures UART1 to receive 2048 bytes of

serial data that will then be placed in the on-chip

SRAM. Once the download is complete, execution

jumps to the start of the on-chip SRAM. This

would allow, for example, code to be downloaded

to program system FLASH during a product’s

manufacturing process. See Section , “Appendix B:

Boot Code” for details of the ROM Boot Code with

comments to describe the stages of execution.

Selection of the Boot ROM option is determined by

the state of the nMEDCHG pin during a power on

reset. If nMEDCHG is high while nPOR is active,

then the CS89712 will boot from an external mem-

ory device connected to CS[0] (normal boot mode).

If nMEDCHG is low, then the boot will be from the

on-chip ROM. Note that in both cases, following

the de-assertion of nPOR, the CS89712 will be in

the Standby State and require a low-to-high transi-

tion on the external WAKEUP pin in order to actu-

ally start the boot sequence.

The effect of booting from the on-chip Boot ROM

is to reverse the decoding for all chip selects inter-

nally. Table 11 shows this decoding. The control

signal for the boot option is latched by nPOR,

which means that the remapping of addresses and

bus widths will continue to apply until nPOR is as-

serted again. After booting from the Boot ROM,

the contents of the Boot ROM can be read back

from address 0x0000.0000 onwards, and in normal

state of operation the Boot ROM contents can be

read back from address range 0x7000.0000.

2.10 Memory Map

The lower 2 GByte of the address space is allocated

to memory. The 512 MBytes of address space from

Interrupt

Input State

Operating State

Latency

Idle State

Latency

Standby State Latency

nEXTFIQ

Not deglitched; must be

active for 251 clock

cycles to ensure detec-

tion

Worst-case 3.4

µsec

at 74 MHz

Worst-case 251

clocks: if only

single cycle

instructions, less

than 1

µsec

Including PLL / osc. settling time, ~

0.25 sec when FASTWAKE = 0, or

approx. 500 µsec when FASTWAKE = 1

nEINT1–2

Not deglitched

Worst-case 3.4

µsec

at 74 MHz

As above

nMEDCHG

Deglitched by 16 kHz

clock; must be active

for at least 125

µs to be

detected

Worst-case latency

of 128

µsec at 74

MHz

Worst-case

µsec: if only

single cycle

instructions,

125

µsec

As above

Table 10. External Interrupt Source Latencies

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