CS89712 datasheet(88/170 Pages) CIRRUS

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CS89712

DS502PP2

3.5.5

SYSFLG2 System Status Register 2 (address 0x8000.1140)

This register is an extension of SYSFLG1, containing status bits for backward compatibility with CL-PS7111. The

bits of the second system status register are defined in Table 41.

21:12

10:7

UTXFF2

URXFE2

Reserved

UBUSY2

Reserved

CKMODE

SS2TXUF

SS2TXFF

SS2RXFE

RESFRM

RESVAL

SS2RXOF

Bit

Description

SS2RXOF: Master / slave SSI2 RX FIFO overflow. This bit is set when a write is attempted to a

full RX FIFO (i.e., when RX is still receiving data and the FIFO is full). This can be cleared in one

of two ways:

1. Empty the FIFO (remove data from FIFO) and then write to SRXEOF location.

2. Disable the RX (affects of disabling the RX will not take place until a full SSI2 clock cycle after

it is disabled)

RESVAL: Master / slave SSI2 RX FIFO residual byte present, cleared by popping the residual

byte into the SSI2 RX FIFO or by a new RX frame sync pulse.

RESFRM: Master / slave SSI2 RX FIFO residual byte present, cleared only by a new RX frame

sync pulse.

SS2RXFE: Master / slave SSI2 RX FIFO empty bit. This will be set if the 16 x 16 RX FIFO is

empty.

SS2TXFF: Master / slave SSI2 TX FIFO full bit. This will be set if the 16 x 16 TX FIFO is full. This

will get cleared when data is removed from the FIFO or the CS89712 is reset.

SS2TXUF: Master / slave SSI2 TX FIFO Underflow bit. This will be set if there is attempt to trans-

mit when TX FIFO is empty. This will be cleared when FIFO gets loaded with data.

CKMODE: This bit reflects the status of the CLKSEL (PE[2]) input, latched on power on reset.

This bit should be low.

UBUSY2: UART2 transmitter busy. This bit is set while UART2 is busy transmitting data; it is

guaranteed to remain set until the complete byte has been sent, including all stop bits.

URXFE2: UART2 receiver FIFO empty. The meaning of this bit depends on the state of the UFI-

FOEN bit in the UART2 bit rate and line control register. If the FIFO is disabled, this bit will be set

when the RX holding register contains is empty. If the FIFO is enabled, the URXFE bit will be set

when the RX FIFO is empty.

UTXFF2: UART2 transmit FIFO full. The meaning of this bit depends on the state of the UFI-

FOEN bit in the UART2 bit rate and line control register. If the FIFO is disabled, this bit will be set

when the TX holding register is full. If the FIFO is enabled, the UTXFF bit will be set when the TX

FIFO is full.

Table 41. SYSFLG2

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