CS89712 datasheet(84/170 Pages) CIRRUS

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CS89712

DS502PP2

SS2RXEN: Receive enable for the synchronous serial interface 2. The receive side of SSI2 will

be disabled until this bit is set. When both SSI2TXEN and SSI2RXEN are disabled, the SSI2

interface will be in a power saving state.

UART2EN: Internal UART2 enable bit. Setting this bit enables the internal UART2.

SS2MAEN: Master mode enable for the synchronous serial interface 2. When low, SSI2 will be

configured for slave mode operation. When high, SSI2 will be configured for master mode opera-

tion. This bit also controls the directionality of the interface pins.

SNZPOL: Snooze State LCD data polarity bit. When low, the LCD controller will put out ‘0000’ on

the DD[3:0] outputs during the blanked parts of the display in Snooze State. When high, ‘1111’

will be output instead. This is to allow the connection of displays with inverse polarity. During nor-

mal Operating State, an inverse polarity display is handled by appropriate programming of the

palette, and this bit will have no effect.

LCDSNZE: This bit is normally set low, but will be automatically set high on entering Snooze

State. While this bit is high, data will be fetched from the on-chip SRAM for the display. When

Snooze State is exited, this bit will have been set high and this will have the effect of causing the

LCD controller to continue to fetch data from the on-chip SRAM, in 1-bit-per-pixel mode, irrespec-

tive of the contents of the LCDCON register. This ensures that the display does not change on

exit from Snooze State, so that if the exit is for a simple update-on-interrupt operation the display

need not be affected. Additional arbitration is included so that the on-chip SRAM can be written to

while the LCDSNZE bit is set after Snooze State. If the exit from Snooze State has occurred

because the device was to be completely woken up, including switching to the main LCD frame

buffer, (whose start address is defined in the FBADDR register) then this can be achieved by writ-

ing a 0 to the LCDSNZE bit, which will cause the CL-CS89712 to start fetching DMA data from

the main buffer and sync up the display at the end of the following frame. The LCDSNZE bit can

never be programmed to 1 by the CPU — the value ‘1’ will be ignored.

Reserved: This bit should be set low.

CLKENSL: CLKEN select. When low, the CLKEN signal will be output on the RUN/CLKEN pin.

When high, the RUN signal will be output on RUN/CLKEN.

BUZFREQ: The BUZFREQ bit is used to select which hardware source will be used as the

source to drive the buzzer output pin. When BUZFREQ = 0, the buzzer signal generated from the

on-chip timer (TC1) is output. When BUZFREQ = 1, a 500 Hz clock is output. See the BZMOD

and the BZTOG bits (SYSCON2) for more details.

Bit

Description

Table 38. SYSCON2 (Continued)

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