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AS1130

Datasheet - D e t a i l e d D e s c r i p t i o n

I²C Interface

The AS1130 supports the I²C serial bus and data transmission protocol in fast mode at 1MHz. The AS1130 operates as a slave on the I²C bus.

The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and generates the START and

STOP conditions. Connections to the bus are made via the open-drain I/O pins SCL and SDA.

Figure 17. I²C Interface Initialization

Figure 18. Bus Protocol

The bus protocol (as shown in Figure 18) is defined as:

- Data transfer may be initiated only when the bus is not busy.

- During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is

HIGH will be interpreted as control signals.

The bus conditions are defined as:

- Bus Not Busy. Data and clock lines remain HIGH.

- Start Data Transfer. A change in the state of the data line, from HIGH to LOW, while the clock is HIGH, defines a START condition.

- Stop Data Transfer. A change in the state of the data line, from LOW to HIGH, while the clock line is HIGH, defines the STOP condition.

- Data Valid. The state of the data line represents valid data, when, after a START condition, the data line is stable for the duration of the

HIGH period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and termi-

nated with a STOP condition. The number of data bytes transferred between START and STOP conditions is not limited and is determined

by the master device. The information is transferred byte-wise and each receiver acknowledges with a ninth-bit. Within the I²C bus speci-

fications a high-speed mode (3.4MHz clock rate) is defined.

- Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The mas-

ter device must generate an extra clock pulse that is associated with this acknowledge bit. A device that acknowledges must pull down the

SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge

clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generat-

ing an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to

enable the master to generate the STOP condition.

- Figure 18 on page 10 details how data transfer is accomplished on the I²C bus. Depending upon the state of the R/W bit, two types of

data transfer are possible:

1

9

8

1

9

8

1

0

AD2

1

0

AD1 AD0 R/W

D15 D14 D13 D12 D11 D10

D9

D8

AD2, AD1 and AD0 are defined by the pin ADDR

(see I²C Device Address Byte on page 12)

SCL

SDA

SDI

SCL

Slave Address

R/W

Direction Bit

START

1

2

6

7

8

9

1

2

3-7

8

9

ACK

MSB

Repeat if More Bytes Transferred

STOP or

Repeated

START

ACK from

Receiver

ACK from

Receiver

ACK