PCIMX258CJM4A datasheet(17/144 Pages) FREESCALE

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i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 3

Freescale Semiconductor

Figure 2 shows the power-up sequence diagram. After POR_B is asserted, Core VDD and NVDDx can be

powered up. After Core VDD and NVDDx are stable, the analog supplies can be powered up.

Figure 2. Power-Up Sequence Diagram

3.2.2

Power-Down Sequence

There are no special requirements for the power-down sequence. All power supplies can be shut down at

the same time.

3.3

Power Characteristics

Table 13 shows values representing maximum current numbers for the i.MX25 under worst case voltage

and temperature conditions. These values are derived from the i.MX25 with core clock speed up to

400 MHz. Additionally, no power saving techniques such as clock gating were implemented when

measuring these values. Common supplies are bundled according to the i.MX25 power-up sequence

requirements. Peak numbers are provided for system designers so that the i.MX25 power supply

requirements are satisfied during startup and transient conditions. Freescale recommends that system

current measurements are taken with customer-specific use-cases to reflect the normal operating

conditions in the end system.

Table 13. Power Consumption

Power Supply

Voltage (V)

Max Current (mA)

QVDD

1.52

360

NVCC_EMI1, NVCC_EMI2

1.9

NVCC_CRM, NVCC_SDIO, NVCC_CSI,

NVCC_NFC, NVCC_JTAG, NVCC_LCDC,

NVCC_MISC

3.6

110

MPLL_VDD, UPLL_VDD

1.65

USBPHY1_VDDA_BIAS, USBPHY1_UPLL_VDD,

USBPHY1_VDDA, USBPHY2_VDD,

OSC24M_VDD, NVCC_ADC

3.3

Analog Supplies

POR_B

QVDD and NVDD

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