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PCIMX258CJM4A Fiches technique(PDF) 61 Page - Freescale Semiconductor, Inc |
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PCIMX258CJM4A Fiches technique(HTML) 61 Page - Freescale Semiconductor, Inc |
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61 / 144 page ![]() i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 3 Freescale Semiconductor 61 3.7.6.1.2 Mobile DDR SDRAM–Specific Parameters The following diagrams and tables specify the timings related to the SDRAMC module which interfaces with the mobile DDR SDRAM. Figure 29. Mobile DDR SDRAM Write Cycle Timing Diagram Table 45. SDRAM Self-Refresh Cycle Timing Parameters ID Parameter Symbol Min. Max. Unit SD16 CKE output delay time tCKS 1.8 — ns Table 46. Mobile DDR SDRAM Write Cycle Timing Parameters1 1 Test condition: Measured using delay line 5 programmed as follows: ESDCDLY5[15:0] = 0x0703. ID Parameter Symbol Min. Max. Unit SD17 DQ and DQM setup time to DQS tDS 0.95 — ns SD18 DQ and DQM hold time to DQS tDH 0.95 — ns SD19 Write cycle DQS falling edge to SDCLK output delay time tDSS 1.8 — ns SD20 Write cycle DQS falling edge to SDCLK output hold time tDSH 1.8 — ns SDCLK SDCLK DQS (output) DQ (output) DQM (output) Data Data Data Data Data Data Data Data DM DM DM DM DM DM DM DM SD17 SD17 SD17 SD17 SD18 SD18 SD18 SD18 SD19 SD20 |
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