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PCIMX258CJM4A Fiches technique(PDF) 93 Page - Freescale Semiconductor, Inc |
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PCIMX258CJM4A Fiches technique(HTML) 93 Page - Freescale Semiconductor, Inc |
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93 / 144 page ![]() i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 3 Freescale Semiconductor 93 3.7.12 Liquid Crystal Display Controller (LCDC) Timing Figure 65 and Figure 66 show LCDC timing in non-TFT and TFT mode respectively, and Table 69 and Table 70 list the timing parameters used in the associated figures. Figure 65. LCDC Non-TFT Mode Timing Diagram Table 69. LCDC Non-TFT Mode Timing Parameters ID Description Min. Max. Unit T1 Pixel clock period 22.5 1000 ns T2 HSYNC width 1 — T1 1 T is pixel clock period T3 LD setup time 5 — ns T4 LD hold time 5 — ns T5 Wait between HSYNC and VSYNC rising edge 2 — T1 T6 Wait between last data and HSYNC rising edge 1 — T1 Line 1 Line 2 Line n Line 1 VSYNC HSYNC HSYNC LSCLK LD T1 T2 T3 T4 T5 T6 |
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