PCIMX258CJM4A datasheet(47/144 Pages) FREESCALE

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i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 3

Freescale Semiconductor

3.7.2.2

Multiword DMA (MDMA) Mode Timing

Figure 13 and Figure 14 show the timing for MDMA read and write modes, respectively.

Figure 13. MDMA Read Mode Timing

Figure 14. MDMA Write Mode Timing

To meet timing requirements, a number of timing parameters must be controlled. See Table 36 for details

on timing parameters for MDMA read and write modes.

Table 36. Timing Parameters for MDMA Read and Write Modes

ATA

Parameter

MDMA Read1

and Write2

Timing

Parameters

Relation

Adjustable

Parameter(s)

tm, ti

tm(min.) = ti(min.) = time_m

× T – (tskew1 + tskew2 + tskew5)

time_m

td, td1

td1(min.) = td(min.) = time_d

× T – (tskew1 + tskew2 + tskew6)

time_d

tk(min.) = time_k

× T – (tskew1 + tskew2 + tskew6)

time_k

—

t0(min.) = (time_d + time_k)

× T

time_d, time_k

tg(read)

tgr

tgr(min.–read) = tco + tsu + tbuf + tbuf + tcable1 + tcable2

tgr(min.–drive) = td – te(drive)

time_d

tf(read)

tfr

tfr(min.–drive) =0 k

—

tg(write)

—

tg(min.–write) = time_d

× T –(tskew1 + tskew2 + tskew5)

time_d

ADDR

(See note 1)

DIOR

READ Data(15:0)

DMARQ

DMACK

tkjn

tgr

tfr

tk1

ADDR

(See note 1)

DIOW

Write Data(15:0)

DMARQ

DMACK

tkjn

tk1

buffer_en

tm ton td1

toff

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