MFRC522 datasheet(94/96 Pages) NXP

94 / 96 page

MFRC522_33

Product data sheet

PUBLIC

Rev. 3 — 26 October 2009

112133

94 of 96

continued >>

NXP Semiconductors

MFRC522

Contactless reader IC

26. Figures

Fig 1.

Simpliﬁed block diagram of the MFRC522. . . . . . .3

Fig 2.

Detailed block diagram of the MFRC522 . . . . . . . .4

Fig 3.

Pinning conﬁguration HVQFN32 (SOT617-1) . . . .5

Fig 4.

MFRC522 Read/Write mode . . . . . . . . . . . . . . . . .7

Fig 5.

ISO/IEC 14443 A/MIFARE Read/Write mode

communication diagram . . . . . . . . . . . . . . . . . . . . .7

Fig 6.

Data coding and framing according to

ISO/IEC 14443 A . . . . . . . . . . . . . . . . . . . . . . . . . .8

Fig 7.

SPI connection to host . . . . . . . . . . . . . . . . . . . . . .9

Fig 8.

UART connection to microcontrollers. . . . . . . . . .10

Fig 9.

UART read data timing diagram. . . . . . . . . . . . . .12

Fig 10. UART write data timing diagram . . . . . . . . . . . . .14

Fig 11. I2C-bus interface . . . . . . . . . . . . . . . . . . . . . . . . .15

Fig 12. Bit transfer on the I2C-bus . . . . . . . . . . . . . . . . . .16

Fig 13. START and STOP conditions. . . . . . . . . . . . . . . .16

Fig 14. Acknowledge on the I2C-bus . . . . . . . . . . . . . . . .17

Fig 15. Data transfer on the I2C-bus . . . . . . . . . . . . . . . .17

Fig 16. First byte following the START procedure . . . . . .18

Fig 17. Register read and write access . . . . . . . . . . . . . .19

Fig 18. I2C-bus HS mode protocol switch . . . . . . . . . . . .20

Fig 19. I2C-bus HS mode protocol frame . . . . . . . . . . . . .21

Fig 20. Serial data switch for p-driver TX1 and TX2 . . . .25

Fig 21. Overview of MFIN and MFOUT signal routing . . .26

Fig 22. Quartz crystal connection . . . . . . . . . . . . . . . . . .31

Fig 23. Oscillator start-up time. . . . . . . . . . . . . . . . . . . . .32

Fig 24. Pin RX input voltage range . . . . . . . . . . . . . . . . .75

Fig 25. Timing diagram for SPI . . . . . . . . . . . . . . . . . . . .76

Fig 26. Timing for Fast and Standard mode devices

on the I2C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . .77

Fig 27. Typical application diagram . . . . . . . . . . . . . . . . .78

Fig 28. Output test signals TestDAC1 on pin AUX1 and

TestDAC2 on pin AUX2 . . . . . . . . . . . . . . . . . . . .81

Fig 29. Output test signals Corr1 on pin AUX1 and

MinLevel on pin AUX2 . . . . . . . . . . . . . . . . . . . . .82

Fig 30. Output ADC channel I on pin AUX1 and ADC

channel Q on pin AUX2 . . . . . . . . . . . . . . . . . . . .82

Fig 31. Output RxActive on pin AUX1 and TxActive

on pin AUX2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

Fig 32. Received data stream on pins AUX1 and AUX2 .84

Fig 33. Package outline SOT617-1 (HVQFN32) . . . . . . .85

Fig 34. Packing information 1 tray . . . . . . . . . . . . . . . . . .86

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