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H8SX/1663M Fiches technique(PDF) 84 Page - Renesas Technology Corp |
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H8SX/1663M Fiches technique(HTML) 84 Page - Renesas Technology Corp |
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84 / 1504 page ![]() Section 2 CPU Rev. 2.00 Sep. 24, 2008 Page 52 of 1468 REJ09B0412-0200 2.7.1 Instructions and Addressing Modes Table 2.2 indicates the combinations of instructions and addressing modes that the H8SX CPU can use. Table 2.2 Combinations of Instructions and Addressing Modes (1) Addressing Mode Classifi- cation Instruction Size #xx Rn @ERn @(d,ERn) @(d, RnL.B/ Rn.W/ ERn.L) @ −ERn/ @ERn +/ @ERn −/ @ +ERn @aa:8 @aa:16/ @aa:32 — B/W/L S SD SD SD SD SD SD MOV B S/D S/D MOVFPE, MOVTPE B S/D S/D* 1 POP, PUSH W/L S/D S/D* 2 LDM, STM L S/D S/D* 2 Data transfer MOVA* 4 B/W S S S S S S EEPMOV B SD* 3 MOVMD B/W/L SD* 3 Block transfer MOVSD B SD* 3 B S D D D D D D D B S D D D D D D B D S S S S S S B SD SD SD SD SD ADD, CMP W/L S SD SD SD SD SD SD B S D D D D D D B S D D D D D D B D S S S S S S B SD SD SD SD SD SUB W/L S SD SD SD SD SD SD B/W/L S SD B/W/L S SD ADDX, SUBX B/W/L S SD* 5 INC, DEC B/W/L D ADDS, SUBS L D DAA, DAS B D MULXU, DIVXU B/W S:4 SD Arithmetic operations MULU, DIVU W/L S:4 SD |
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