H8SX1663 datasheet(122/1158 Pages) RENESAS

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Section 3 MCU Operating Modes

Rev.1.00 Jun. 07, 2006 Page 70 of 1102

REJ09B0294-0100

3.3

Operating Mode Descriptions

3.3.1

Mode 2

This is the boot mode for the flash memory. The LSI operates in the same way as in mode 7

except for programming and erasing of the flash memory. For details, see section 21, Flash

Memory (0.18-

µm F-ZTAT Version).

3.3.2

Mode 4

The CPU operating mode is advanced mode in which the address space is 16 Mbytes, and the on-

chip ROM is disabled.

The initial bus width mode immediately after a reset is 16 bits, with 16-bit access to all areas.

Ports D, E, and F function as an address bus, ports H and I function as a data bus, and parts of

ports A and B function as bus control signals. However, if all areas are designated as an 8-bit

access space by the bus controller, the bus mode switches to eight bits, and only port H functions

as a data bus.

3.3.3

Mode 5

The CPU operating mode is advanced mode in which the address space is 16 Mbytes, and the on-

chip ROM is disabled.

The initial bus width mode immediately after a reset is eight bits, with 8-bit access to all areas.

Ports D, E, and F function as an address bus, port H functions as a data bus, and parts of ports A

and B function as bus control signals. However, if any area is designated as a 16-bit access space

by the bus controller, the bus width mode switches to 16 bits, and ports H and I function as a data

bus.

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