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H8SX1663 Fiches technique(PDF) 92 Page - Renesas Technology Corp |
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H8SX1663 Fiches technique(HTML) 92 Page - Renesas Technology Corp |
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92 / 1158 page ![]() Section 2 CPU Rev.1.00 Jun. 07, 2006 Page 40 of 1102 REJ09B0294-0100 2.7.1 Instructions and Addressing Modes Table 2.2 indicates the combinations of instructions and addressing modes that the H8SX CPU can use. Table 2.2 Combinations of Instructions and Addressing Modes (1) Addressing Mode Classifi- cation Instruction Size #xx Rn @ERn @(d,ERn) @(d, RnL.B/ Rn.W/ ERn.L) @ −ERn/ @ERn +/ @ERn −/ @ +ERn @aa:8 @aa:16/ @aa:32 — Data transfer MOV B/W/L S SD SD SD SD SD SD B S/D S/D MOVFPE, MOVTPE* 12 B S/D S/D* 1 POP, PUSH W/L S/D S/D* 2 LDM, STM L S/D S/D* 2 MOVA* 4 B/W S S S S S S EEPMOV B SD* 3 Block transfer MOVMD B/W/L SD* 3 MOVSD B SD* 3 ADD, CMP B S D D D D D D D B S D D D D D D B D S S S S S S B SD SD SD SD SD W/L S SD SD SD SD SD SD Arithmetic operations SUB B S D D D D D D B S D D D D D D B D S S S S S S B SD SD SD SD SD W/L S SD SD SD SD SD SD ADDX, SUBX B/W/L S SD B/W/L S SD B/W/L S SD* 5 INC, DEC B/W/L D ADDS, SUBS L D DAA, DAS B D MULXU, DIVXU B/W S:4 SD MULU, DIVU W/L S:4 SD |
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