H8SX1663 datasheet(63/1158 Pages) RENESAS

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Section 1 Overview

Rev.1.00 Jun. 07, 2006 Page 11 of 1102

REJ09B0294-0100

Classification

Abbreviation

Pin No.

(FP-144LV)

I/O

Description

Data bus

D15

D14

D13

D12

D11

D10

Input/

output

Bidirectional data bus. These pins also output

addresses when accessing the address/data

multiplexed I/O interface space.

Bus control

BREQ

136

Input

External bus masters request the bus by this

signal.

BREQO

134

Output The internal bus masters request the bus to

access the external space in the external bus

released state.

BACK

135

Output Bus acknowledge signal which indicates that

the bus has been released.

BS-A/BS-B

134/140

Output Indicates the start of a bus cycle.

140

Output Strobe signal which indicates that the output

address on the address bus is valid when

accessing the basic bus interface or byte

control SRAM interface space.

140

Output This signal is used to hold the address when

accessing the address/data multiplexed I/O

interface space.

139

Output Strobe signal to indicates that the basic bus

interface space is being read from.

RD/

WR-A/RD/WR-B 135/132

Output Indicates the direction (input/output) of the

data bus.

LHWR

138

Output Strobe signal which indicates that the upper

byte (D15 to D8) is valid when accessing the

basic bus interface space.

LLWR

137

Output Strobe signal which indicates that the lower

byte (D7 to D0) is valid when accessing the

basic bus interface space.

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