H8SX1663 datasheet(64/1158 Pages) RENESAS

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Section 1 Overview

Rev.1.00 Jun. 07, 2006 Page 12 of 1102

REJ09B0294-0100

Classification

Abbreviation

Pin No.

(FP-144LV)

I/O

Description

Bus control

LUB

138

Output Strobe signal which indicates that the upper

byte (D15 to D8) is valid when accessing the

byte control SRAM interface space.

LLB

137

Output Strobe signal which indicates that the lower

byte (D7 to D0) is valid when accessing the

byte control SRAM interface space.

CS0

CS1

CS2-A/CS2-B

CS3-A

CS4-A/CS4-B

CS5-A/CS5-B

CS6-A/CS6-B/CS6-D

CS7-A/CS7-B

144

2/1

144/130

1/144

2/1/132

3/1

Output Select signals for areas 7 to 0.

WAIT

136

Input

Requests wait cycles when accessing the

external space.

RAS

Output

•

Row address strobe signal for DRAM

when area 2 is specified as DRAM

interface space.

•

Row address strobe signal when area 2 is

specified as synchronous DRAM interface

space.

CAS

Output Column address strobe signal when area 2 is

specified as synchronous DRAM interface

space.

130

Output

•

Write enable signal for DRAM space.

•

Write enable signal when area 2 is

specified as synchronous DRAM interface

space.

OE/CKE

131

Output

•

Output enable signal for DRAM interface

space.

•

Clock enable signal for synchronous

DRAM interface space.

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