H8SX1663 datasheet(106/1158 Pages) RENESAS

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Section 2 CPU

Rev.1.00 Jun. 07, 2006 Page 54 of 1102

REJ09B0294-0100

2.7.3

Basic Instruction Formats

The H8SX CPU instructions consist of 2-byte (1-word) units. An instruction consists of an

operation field (op field), a register field (r field), an effective address extension (EA field), and a

condition field (cc).

Figure 2.14 shows examples of instruction formats.

NOP, RTS, etc.

ADD.B Rn, Rm, etc.

MOV.B @(d:16, Rn), Rm, etc.

(1) Operation field only

(2) Operation field and register fields

(3) Operation field, register fields, and effective address extension

EA (disp)

(4) Operation field, effective address extension, and condition field

EA (disp)

BRA d:16, etc

Figure 2.14 Instruction Formats

• Operation Field

Indicates the function of the instruction, and specifies the addressing mode and operation to be

carried out on the operand. The operation field always includes the first four bits of the

instruction. Some instructions have two operation fields.

• Register Field

Specifies a general register. Address registers are specified by 3 bits, data registers by 3 bits or

4 bits. Some instructions have two register fields. Some have no register field.

• Effective Address Extension

8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement.

• Condition Field

Specifies the branch condition of Bcc instructions.

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