H8S2245 datasheet(610/818 Pages) RENESAS

No de pièce	H8S2245

Description	Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2200 Series

PDF	818 Pages

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Fabricant	RENESAS [Renesas Technology Corp]

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Section 18 Power-Down Modes

Rev.3.00 Mar. 26, 2007 Page 568 of 772

REJ09B0355-0300

Oscillator

RES

STBY

Oscillation

stabilization

time

tOSC1

Reset

exception

handling

Figure 18.3 Hardware Standby Mode Timing (Example)

18.8

φφφφ Clock Output Disabling Function

Output of the

φ clock can be controlled by means of the PSTOP bit in SCKCR and DDR for the

corresponding port. When the PSTOP bit is set to 1, the

φ clock stops at the end of the bus cycle,

and

φ output goes high. φ clock output is enabled when the PSTOP bit is cleared to 0. When DDR

for the corresponding port is cleared to 0,

φ clock output is disabled and input port mode is set.

Table 18.5 shows the state of the

φ pin in each processing mode.

Table 18.5

φφφφ Pin State in Each Processing Mode

DDR

PSTOP

Normal Mode

Sleep Mode

Software

Standby Mode

Hardware

Standby Mode

High impedance High impedance High impedance High impedance

φ output

Fixed high

High impedance

Fixed high

High impedance

Legend:

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