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H8S2245 Fiches technique(PDF) 398 Page - Renesas Technology Corp |
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H8S2245 Fiches technique(HTML) 398 Page - Renesas Technology Corp |
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398 / 818 page ![]() Section 9 16-Bit Timer Pulse Unit (TPU) Rev.3.00 Mar. 26, 2007 Page 356 of 772 REJ09B0355-0300 Contention between Buffer Register Write and Compare Match If a compare match occurs in the T2 state of a TGR write cycle, the data transferred to TGR by the buffer operation will be the data prior to the write. Figure 9.48 shows the timing in this case. Compare match signal Write signal Address φ Buffer register address Buffer register TGR write cycle T1 T2 N TGR N M Buffer register write data Figure 9.48 Contention between Buffer Register Write and Compare Match |
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