ST52T410 datasheet(18/84 Pages) STMICROELECTRONICS

18 / 84 page

ST52T410/ST52T420/E420

18/84

The STACK POINTER indicates the first level

available to store data. When a subroutine call or

interrupt request occurs, the content of the PC and

the current set of flags are stored into the level

located by the STACK POINTER.

When a interrupt return occurs (RETI instruction),

the data stored in the highest stack level is

restored back into the PC and current flags.

Instead, when a subroutine return occurs (RET

instruction) the data stored in the highest stack

level are restored in the PC not affecting the flags.

These operating modes are illustrated in Figure

2.4.

Note:

The user must pay close attention to avoid

overwriting RAM locations where the STACK could

be stored.

2.3.2 Input Registers Bench.

The Input Registers (IR) bench consists of 18 8-bit

registers containing data or the status of the

peripherals.

All the registers can be specified by using a

decimal address (for example, 0 identifies the first

The assembler instruction:

LDRI RAM_Reg. IR_i

loads the value of the i-th IR in the RAM location

identified by the RAM_Reg address.

The first input register is dedicated to store the

value of the stack pointer. The next 8 registers

(ADC_OUT_0:7) of the IR are dedicated to the 8

converted

values

deriving

from

the

ADC

(ST52x420 only). The last 9 Input Registers

contain data from the I/O ports and PWM/Timers.

The following table summarizes the IR address

and the relative peripherals. In order to simplify the

concept, a mnemonic name is assigned to the

registers.

The

same

name

used

VISUALSTUDIO® development tools

Figure 2.4 Stack Operation

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