ST20-GP1 datasheet(10/116 Pages) STMICROELECTRONICS

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ST20-GP1

10/116

Serial communications

The

ST20-GP1

has

two

UARTs

(Asynchronous

Serial

Controllers

(ASCs))

for

serial

communication. The UARTs provide an asynchronous serial interface and can be programmed to

support a range of baud rates and data formats, for example, data size, stop bits and parity.

There is one OS-Link on the ST20-GP1 which acts as a DMA engine independent of the CPU. The

OS-Link uses an asynchronous bit-serial (byte-stream) protocol, each bit received is sampled ﬁve

times, hence the term

oversampled link (OS-Link). The OS-Link provides a pair of channels, one

input and one output channel. The link is used for:

•

bootstrapping during development,

•

debugging,

•

communicating with OS-Link peripherals or other ST20 devices.

Interrupt subsystem

The ST20-GP1 interrupt subsystem supports ﬁve prioritized interrupts. Three interrupts are

connected to on-chip peripherals (2 for the UARTs, 1 for the programmable IO) and two are

available as external interrupt pins.

All interrupts are at a higher priority than the high priority process queue. Each interrupt level has a

higher priority than the previous and each level supports only one software handler process.

Note that interrupt handlers must not prevent the GPS DSP data trafﬁc from being handled. During

continuous operation this has 1 ms latency and is not a problem, but during initial acquisition it has

a 32

µs rate and thus all interrupts must be disabled except if used to stop GPS operation.

Byte-wide parallel port

The byte-wide parallel port is provided to communicate with an external device. It transfers a byte

at a time, operating half duplex in the program-selected direction.

Parallel IO module

Six bits of parallel IO are provided. Each bit is programmable as an output or an input. Edge

detection logic is provided which can generate an interrupt on any change of an input bit.

System services module

The ST20-GP1 system services module includes:

•

reset, initialization and error port.

•

phase locked loop (PLL) — accepts 16.368 MHz input and generates all the internal high

frequency clocks needed for the CPU and the OS-Link.

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