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Flip Chip SiP (Cont.)

The devices in this application space have low to

medium I/O count and are fairly small in size. This, in

conjunction with the solder mask being removed from

underneath the die (which increases the standoff),

makes these products viable candidates for transfer

molding applications. Thus, the underfill operation

can be eliminated from the process flow which leads

to significant cost savings. Studies have shown that

transfer molded packages are more reliable (MSL as

well as extended reliability testing such as temperature

cycling, HAST, etc.) than their underfilled counterparts

due to balanced die stresses and better solder CTE

matching.

Copper pillar or solder bump for GaAs and Si

applications in LGA or BGA format

Wafer Level Packaging – CSPnl

CSPnl is a true wafer level package to address improved

second-level board reliability, that incorporates a thin

film redistribution process to route the pads to JEDEC

standard pitches. Standard CSP solder bumps are

formed on the re-routed pads. The CSPnl is designed

to utilize standard surface mount assembly and

reflow techniques. By using standard SMT placement

equipment, and avoiding the need for underfill, the end

user experiences many of the cost benefits associated

with other JEDEC standard area array packages.

Features

f

Incorporates standard JEDEC pitches and CSP solder

ball diameters

f

Compatible with standard SMT assembly and test

techniques

f

Utilizes cost-effective thin film redistribution

technologies

f

Backside laser mark compatible

f

No need for underfill in most applications

f

Full turnkey CSPnl processing including test and tape

& reel support

f

Eutectic lead-free solder balls

f

Available with polyimide repassivation

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Qualified and in volume production

f

Proven reliability; exceeds all current handset

mechanical reliability tests including drop, bend and

key punch