What Is Flip Chip?

Flip chip is not a specific package (like SOIC), or even a package type (like

BGA). Flip chip describes the method of electrically connecting the die to

the package carrier. The package carrier, either substrate or leadframe,

then provides the connection from the die to the exterior of the package. In

“standard” packaging, the interconnection between the die and the carrier

is made using wire. The die is attached to the carrier face up, then a wire is

bonded first to the die, then looped and bonded to the carrier. Wires are

typically 1-5 mm in length and 15-35 µm in diameter.

In contrast, the interconnection between the die and carrier in flip chip

packaging is made through a conductive “bump” that is placed directly

on the die surface. The bumped die is then “flipped over” and placed face

down, with the bumps connecting to the carrier directly. A bump is typically

60-100 µm high and 80-125 µm in diameter, while a copper pillar (CuP)

bump is typically a 40 µm high Cu pillar capped with SnAg.

The flip chip connection is generally formed one of two ways: using

solder or using conductive adhesive. By far, the most common packaging

interconnect is solder. Current solder options are eutectic Sn/Pb or lead-

free (98.2% Sn, 1.8% Ag) compositions. The solder bumped die is attached

to a substrate by a solder reflow process, very similar to the process used

to attach BGA balls to the package exterior. After the die is soldered,

underfill is added between the die and the substrate.

Underfill is a specially engineered epoxy that fills the area between the die

and the carrier, surrounding the solder bumps. It is designed to control the

stress in the solder joints caused by the difference in thermal expansion

between the silicon die and the carrier. Once cured, the underfill absorbs

the stress, reducing the strain on the solder bumps, greatly increasing the

life of the finished package. The chip attach and underfill steps are the

basics of flip chip interconnect. Beyond this, the remainder of package

construction surrounding the die can take many forms and can generally

utilize existing manufacturing processes and package formats.

Demand for flip chip interconnect technology is being driven by a

number of factors from all corners of the silicon industry. To support

this demand, Amkor is committed to being the leading provider of

Flip Chip in Package (FCiP) technology. By partnering with proven

industry leaders, Amkor has brought high volume packaging and

assembly to the subcontract market. Since being the first OSAT to

provide FCiP solutions in 1999, Amkor has continued to introduce

innovative packaging solutions utilizing flip chip interconnect and

offers the broadest range of FCiP solutions on the market.

Flip Chip Packaging

TECHNOLOGY SOLUTIONS

BENEFITS OF FLIP CHIP

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Reduced signal inductance – because

the interconnect is much shorter

in length (0.1 mm vs. 1-5 mm), the

inductance of the signal path is greatly

reduced. This is a key factor in high

speed communication and switching

devices

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Reduced power/ground inductance –

by using flip chip interconnect, power

can be brought directly into the core

of the die, rather than having to be

routed to the edges. This greatly

decreases the noise of the core power,

improving performance of the silicon

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Higher signal density – the entire

surface of the die can be used

for interconnect, rather than just

the edges. This is similar to the

comparison between QFP and BGA

packages. Because flip chip can

connect over the surface of the die, it

can support vastly larger numbers of

interconnects on the same die size

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Die shrink – for pad limited die (die

where size is determined by the edge

space required for bond pads), the

size of the die can be reduced, saving

silicon cost

f

Reduced package footprint – in some

cases, the total package size can be

reduced using flip chip. This can be

achieved by either reducing the die

to package edge requirements, since

no extra space is required for wires,

or in utilizing higher density substrate

technology, which allows for reduced

package pitch