Flip Chip BGA Package (Cont.)

Technology

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Substrates

▷ 4-18 layer laminate build-up substrates

▷ High CTE ceramic

▷ Coreless

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Bump types

▷ Eutectic Sn/Pb

▷ Pb-free

▷ Cu pillar (array and fine-pitch peripheral)

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Package formats

▷ Bare die

▷ Lidded

▷ Molded

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90 µm minimum array bump pitch

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<100 µm minimum peripheral bump pitch

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Die sizes up to 29 mm

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Package sizes from 10 mm to 66 mm (85 mm in

development)

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0.4 mm, 0.5 mm, 0.65 mm, 0.8 mm and 1.0 mm

pitch BGA footprints

FCBGA/LGA (Bare die)

Flip chip packaging solution for most graphics, PC

chipset and low-end ASIC applications

fcCeramic CBGA/CLGA/CLLGA/solder

column interposer

Original packaging solution for flip chip products

Flip Chip CSP Package

Features

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Designed for high-frequency applications

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Target market – cell phones, handheld electronics

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Thin-core laminate or ceramic package construction

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Overmolded for handling and second level reliability

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Accommodates package sizes from 3 mm to 15 mm

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Flip chip bump pitches of 150 µm mininum for

peripheral array, 250 µm minimum for area array

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Available in 0.5-1.0 mm BGA ball pitch, as well as

LGA interconnect

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Minimum package thickness of 0.80 mm for LGA

interconnect, 1.0 mm for 0.5 mm BGA pitch and 1.2

mm for 0.8 mm BGA pitch

fcCSP

Flip chip solution for CSP package technology

Flip Chip System in Package (SiP)

Flip chip SiP package is an extension of the SiP product

offering from Amkor with the device interconnect

technology being flip chip rather than traditional

wirebond interconnects. The package may contain

multiple passive components, silicon and/or GaAs

devices bumped with traditional solder bumps or solder

coated copper pillar bumps housed in 2-layer or 4-layer

high-density substrates. This package format is gaining

traction in RF power amplifier and RF front end module

applications for size, performance and cost reasons.

Controlled collapse of the bumps leads to predictable

interconnect impedance and hence more stable

product performance. The low-solder volume in the

‘wetting tip’ allows for the elimination of the solder

mask from underneath the die which reduces the

substrate complexity and cost and removes a major

barrier for adopting the fine pitch FC interconnection

technology in the RF application space. Flip chip

interconnection may also preclude the need for

wafer backgrinding (for mold cap thickness 0.9 mm)

which leads to further reduction in product cost and

simplification of the process flow.