TMD2621 datasheet(32/59 Pages) OSRAM

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Datasheet, Public

Page 31

[v4-00] 2023-Apr-12

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TMD2621 − Register Overview

VSYNC_CFG Register (Address 0xB1)

Figure 44:

VSYNC_CFG Register

Addr: 0xB1

VSYNC_CFG

Bit

Bit Name

Default

Access

Bit Description

7:6

Reserved

Reserved. Must be set to default value.

5:4

VSYNC_CHG_

DET_STP

VSYNC period change detection step.

Once VSYNC period changes from previous cycle

by step of period mentioned in the following

table, VSYNC_CHG_INT interrupt is generated if

VSIEN=1.

VSYNC_PRD ={VSYNC_PRD_H, VSYNC_PRD_L}

Value

Timing

0Compare with VSYNC_PRD[15:10]

Compare with VSYNC_PRD[15:9]

2Compare with VSYNC_PRD[15:11]

3Compare with VSYNC_PRD[15:12]

INT_VSYNC_EN

Enables internal VSYNC. It will be cleared

automatically when VSYNC signal is detected on

the device VSYNC pin.

2VSYNC_INVERT

This bit inverts VSYNC input.

0 – Not inverted;

1 – Inverted;

1:0

VSYNC_WD_TH

VSYNC watch dog time out. The expiration

generates VSYNC_LOST_INT interrupt if

VSIEN=1.

Value

Timing

88.92ms

11.12ms

22.23ms

44.46ms

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